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LMS 2012
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LMS 2012
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#include "csl/cslr.h"Go to the source code of this file.
Macros | |
| #define | CSL_IDEF_INLINE static inline |
| #define | CSL_UPP_PER_CNT 1 |
| Number of UPP instances. More... | |
| #define | CSL_HPI_PER_CNT 1 |
| Number of UHPI instances. More... | |
| #define | CSL_MCASP_PER_CNT 1 |
| Number of McASP instances. More... | |
| #define | CSL_TMR_PER_CNT 4 |
| Number of TIMER instances. More... | |
| #define | CSL_PSC_PER_CNT 2 |
| Number of PSC instances. More... | |
| #define | CSL_UART_PER_CNT 3 |
| Number of UART instances. More... | |
| #define | CSL_SPI_PER_CNT 2 |
| Number of SPI instances. More... | |
| #define | CSL_I2C_PER_CNT 2 |
| Number of I2C instances. More... | |
| #define | CSL_PLLC_PER_CNT 2 |
| Number of PLL instances. More... | |
| #define | CSL_MMCSD_PER_CNT 2 |
| Number of MMCSD instances. More... | |
| #define | CSL_LCDC_PER_CNT 1 |
| Number of LCDC instances. More... | |
| #define | CSL_MCBSP_PER_CNT 2 |
| Number of Mcbsp instances. More... | |
| #define | CSL_EDMA3CC_CNT 2 |
| Number of EDMA3 CC instances. More... | |
| #define | CSL_EDMA3TC_CNT 3 |
| Number of EDMA3 TC instances. More... | |
| #define | CSL_EMIFA_PER_CNT 1 |
| Number of EMIFA instances. More... | |
| #define | CSL_EMIFB_PER_CNT 1 |
| Number of EMIFB instances. More... | |
| #define | CSL_EMAC_PER_CNT 1 |
| Number of EMAC instances. More... | |
| #define | CSL_MDIO_PER_CNT 1 |
| Number of MDIO instances. More... | |
| #define | CSL_EHRPWM_PER_CNT 2 |
| Number of EHRPWM instances. More... | |
| #define | CSL_ECAP_PER_CNT 3 |
| Number of ECAP instances. More... | |
| #define | CSL_CPGMACSSR_PER_CNT 1 |
| Number of CPGMAC instances. More... | |
| #define | CSL_CPPI_PER_CNT 1 |
| Number of CPPI instances. More... | |
| #define | CSL_USB_PER_CNT 2 |
| Number of USB instances. More... | |
| #define | CSL_VPIF_PER_CNT 1 |
| Number of VPIF instances. More... | |
| #define | CSL_INTC_PER_CNT 1 |
| Number of INTC instances. More... | |
| #define | CSL_AINTC_PER_CNT 1 |
| Number of AINTC instances. More... | |
| #define | CSL_SATA_PER_CNT 1 |
| Number of SATA instances. More... | |
| #define | CSL_RTC_PER_CNT 1 |
| Number of RTC instances. More... | |
| #define | CSL_GPIO_PER_CNT 1 |
| Number of GPIO instances. More... | |
| #define | CSL_SYSCFG_PER_CNT 2 |
| Number of SYSCFG instances. More... | |
| #define | CSL_HPI (0) |
| Peripheral Instances of UHPI instances. More... | |
| #define | CSL_MCASP_0 (0) |
| Peripheral Instances of McASP instances. More... | |
| #define | CSL_EDMA3CC_0 (0) |
| Peripheral Instance of EDMA CC instances. More... | |
| #define | CSL_EDMA3CC_1 (1) |
| #define | CSL_EDMA3TC_0 (0) |
| Peripheral Instance of EDMA TC instances. More... | |
| #define | CSL_EDMA3TC_1 (1) |
| #define | CSL_TMR_0 (0) |
| Peripheral Instance of Timer 64 instances. More... | |
| #define | CSL_TMR_1 (1) |
| #define | CSL_TMR_2 (2) |
| #define | CSL_TMR_3 (3) |
| #define | CSL_PSC_0 (0) |
| Peripheral Instances of PSC instances. More... | |
| #define | CSL_PSC_1 (1) |
| #define | CSL_UART_0 (0) |
| Peripheral Instances of UART instances. More... | |
| #define | CSL_UART_1 (1) |
| #define | CSL_UART_2 (2) |
| #define | CSL_SPI_0 (0) |
| Peripheral Instances of SPI instances. More... | |
| #define | CSL_SPI_1 (1) |
| #define | CSL_I2C_0 (0) |
| Peripheral Instances of I2C instances. More... | |
| #define | CSL_I2C_1 (1) |
| #define | CSL_MMCSD_0 (0) |
| Peripheral Instances of MMCSD instances. More... | |
| #define | CSL_MMCSD_1 (1) |
| #define | CSL_LCDC (0) |
| Peripheral Instances of LCDC instances. More... | |
| #define | CSL_PLLC_0 (0) |
| Instance number of PLL controller. More... | |
| #define | CSL_PLLC_1 (1) |
| #define | CSL_EMIFA (0) |
| Peripheral Instance of EMIFA instances. More... | |
| #define | CSL_EMAC (0) |
| Peripheral Instance of EMAC instances. More... | |
| #define | CSL_MDIO (0) |
| Peripheral Instance of MDIO instances. More... | |
| #define | CSL_EHRPWM_0 (0) |
| Peripheral Instance of EHRPWM instances. More... | |
| #define | CSL_EHRPWM_1 (1) |
| #define | CSL_ECAP_0 (0) |
| Peripheral Instance of ECAP instances. More... | |
| #define | CSL_ECAP_1 (1) |
| #define | CSL_ECAP_2 (2) |
| #define | CSL_USB_0 (0) |
| Peripheral Instance of USB instances. More... | |
| #define | CSL_USB_1 (1) |
| #define | CSL_PRUCORE_0 (0) |
| Peripheral Instance of PRU CORE instances. More... | |
| #define | CSL_PRUCORE_1 (1) |
| #define | CSL_PRUINTC (0) |
| Peripheral Instance of PRUINTC instances. More... | |
| #define | CSL_INTC (0) |
| Peripheral Instance of INTC instances. More... | |
| #define | CSL_AINTC (0) |
| Peripheral Instance of AINTC instances. More... | |
| #define | CSL_RTC (0) |
| Peripheral Instance of RTC instances. More... | |
| #define | CSL_GPIO (0) |
| Peripheral Instance of GPIO instances. More... | |
| #define | CSL_ECTL (0) |
| Peripheral Instance of ECTL instances. More... | |
| #define | CSL_SYSCFG (2) |
| Peripheral Instance of SYSCFG instances. More... | |
| #define | CSL_INTC_0_REGS (0x01800000u) |
| Base address of INTC memory mapped registers. More... | |
| #define | CSL_PWRDWN_PDC_REGS (0x01810000u) |
| Base address of PDC memory mapped registers. More... | |
| #define | CSL_SYS_0_SECURITY_ID_REGS (0x01811000u) |
| Base address of SYS - Security ID register. More... | |
| #define | CSL_SYS_0_REV_ID_REGS (0x01812000u) |
| Base address of SYS - Revision ID register. More... | |
| #define | CSL_IDMA_0_REGS (0x01820000u) |
| #define | CSL_EMC_0_REGS (0x01820000u) |
| #define | CSL_CACHE_0_REGS (0x01840000u) |
| #define | CSL_EDMA30CC_0_REGS (0x01C00000u) |
| Base address of Channel controller memory mapped registers. More... | |
| #define | CSL_EDMA30TC_0_REGS (0x01C08000u) |
| Base address of Transfer controller memory mapped registers. More... | |
| #define | CSL_EDMA30TC_1_REGS (0x01C08400u) |
| #define | CSL_PSC_0_REGS (0x01C10000u) |
| Base address of PSC memory mapped registers. More... | |
| #define | CSL_PLLC_0_REGS (0x01C11000u) |
| PLL controller instance o module address. More... | |
| #define | CSL_SYSCFG_0_REGS (0x01C14000u) |
| Base address of DEV memory mapped registers. More... | |
| #define | CSL_TMR_0_REGS (0x01C20000u) |
| Base address of TIMER memory mapped registers. More... | |
| #define | CSL_TMR_1_REGS (0x01C21000u) |
| #define | CSL_I2C_0_REGS (0x01C22000u) |
| Base address of I2C memory mapped registers. More... | |
| #define | CSL_RTC_0_REGS (0x01C23000u) |
| Base address of RTC memory. More... | |
| #define | CSL_MMCSD_0_REGS (0x01C40000u) |
| Base address of MMCSD memory mapped registers. More... | |
| #define | CSL_SPI_0_REGS (0x01C41000u) |
| Base address of SPI memory mapped registers. More... | |
| #define | CSL_UART_0_REGS (0x01C42000u) |
| Base address of UART memory mapped registers. More... | |
| #define | CSL_MCASP_0_CTRL_REGS (0x01D00000u) |
| Base address of McASP memory mapped registers. More... | |
| #define | CSL_MCASP_0_FIFO_REGS (0x01D01000u) |
| #define | CSL_MCASP_0_DATA_REGS (0x01D02000u) |
| #define | CSL_UART_1_REGS (0x01D0C000u) |
| Base address of UART memory mapped registers. More... | |
| #define | CSL_UART_2_REGS (0x01D0D000u) |
| #define | CSL_MCBSP_0_CTRL_REGS (0x01D10000u) |
| Base address of McBSP memory mapped registers. More... | |
| #define | CSL_MCBSP_0_FIFO_REGS (0x01D10800u) |
| #define | CSL_MCBSP_0_DATA_REGS (0x01F10000u) |
| #define | CSL_MCBSP_1_CTRL_REGS (0x01D11000u) |
| Base address of McASP memory mapped registers. More... | |
| #define | CSL_MCBSP_1_FIFO_REGS (0x01D11800u) |
| #define | CSL_MCBSP_1_DATA_REGS (0x01F10000u) |
| #define | CSL_USB_0_REGS (0x01E00000u) |
| Base address of USB memory. More... | |
| #define | CSL_USB_1_REGS (0x01E25000u) |
| #define | CSL_HPI_0_REGS (0x01E10000u) |
| Base address of HPI memory mapped registers. More... | |
| #define | CSL_LCDC_0_REGS (0x01E13000u) |
| Base address of LCDC memory mapped registers. More... | |
| #define | CSL_UPP_0_REGS (0x01E16000u) |
| Base address of UPP memory mapped registers. More... | |
| #define | CSL_VPIF_0_REGS (0x01E17000u) |
| Base address of VPIF memory mapped registers. More... | |
| #define | CSL_SATA_0_REGS (0x01E18000u) |
| Base address of SATA memory mapped registers. More... | |
| #define | CSL_PLLC_1_REGS (0X01E1A000u) |
| PLL controller instance 1 module address. More... | |
| #define | CSL_MMCSD_1_REGS (0x01E1B000u) |
| Base address of MMCSD memory mapped registers. More... | |
| #define | CSL_EMAC_DSC_CTRL_MOD_RAM (0x01E20000u) |
| Base address of EMAC memory. More... | |
| #define | CSL_EMAC_DSC_CTRL_MOD_REG (0x01E22000u) |
| #define | CSL_EMAC_DSC_CONTROL_REG (0x01E23000u) |
| #define | CSL_MDIO_0_REGS (0x01E24000u) |
| #define | CSL_PRUCORE_0_REGS (0x01C37000u) |
| Base address of PRU Core Regsiters. More... | |
| #define | CSL_PRUCORE_1_REGS (0x01C37800u) |
| #define | CSL_PRUINTC_0_REGS (0x01C34000u) |
| Base address of PRU Interrupt Controller Registers. More... | |
| #define | CSL_GPIO_0_REGS (0x01E26000u) |
| Base address of GPIO memory mapped registers. More... | |
| #define | CSL_PSC_1_REGS (0x01E27000u) |
| Base address of PSC memory mapped registers. More... | |
| #define | CSL_I2C_1_REGS (0x01E28000u) |
| Base address of I2C memory mapped registers. More... | |
| #define | CSL_SYSCFG_1_REGS (0x01E2C000u) |
| Base address of syscfg registers. More... | |
| #define | CSL_EDMA31CC_0_REGS (0x01E30000u) |
| Base address of Channel controller memory mapped registers. More... | |
| #define | CSL_EDMA31TC_0_REGS (0x01E38000u) |
| Base address of Transfer controller memory mapped registers. More... | |
| #define | CSL_EHRPWM_0_REGS (0x01F00000u) |
| Base address of EPWM memory mapped registers. More... | |
| #define | CSL_EHRPWM_1_REGS (0x01F02000u) |
| #define | CSL_HRPWM_0_REGS (0x01F01000u) |
| Base address of EPWM memory mapped registers. More... | |
| #define | CSL_HRPWM_1_REGS (0x01F03000u) |
| #define | CSL_ECAP_0_REGS (0x01F06000u) |
| Base address of ECAP memory mapped registers. More... | |
| #define | CSL_ECAP_1_REGS (0x01F07000u) |
| #define | CSL_ECAP_2_REGS (0x01F08000u) |
| #define | CSL_TMR_2_REGS (0x01F0C000u) |
| Base address of TIMER memory mapped registers. More... | |
| #define | CSL_TMR_3_REGS (0x01F0D000u) |
| #define | CSL_SPI_1_REGS (0x01F0E000u) |
| Base address of SPI memory mapped registers. More... | |
| #define | CSL_EMIFA_0_REGS (0x68000000u) |
| Base address of EMIFA memory mapped registers. More... | |
| #define | CSL_EMIFA_CS0_ADDR (0x40000000u) |
| Base address of EMIFA_CS0 memory. More... | |
| #define | CSL_EMIFA_CS2_ADDR (0x60000000u) |
| Base address of EMIFA_CS2 memory. More... | |
| #define | CSL_EMIFA_CS3_ADDR (0x62000000u) |
| Base address of EMIFA_CS3 memory. More... | |
| #define | CSL_EMIFA_CS4_ADDR (0x64000000u) |
| Base address of EMIFA_CS4 memory. More... | |
| #define | CSL_EMIFA_CS5_ADDR (0x66000000u) |
| Base address of EMIFA_CS5 memory. More... | |
| #define | CSL_DDR2_0_CTRL_REGS (0xB0000000u) |
| Base address of DDR memory mapped registers. More... | |
| #define | CSL_DDR2_0_DATA_REGS (0xC0000000u) |
| #define | CSL_AINTC_0_REGS (0xFFFEE000u) |
| Base address of AINTC memory mapped registers. More... | |
| #define | CSL_MEMPROT_L2_REGS (0x00800000u) |
| Base address of UMC Memory protection registers. More... | |
| #define | CSL_MEMPROT_L1P_REGS (0x00E00000u) |
| Base address of PMC memory Protection registers. More... | |
| #define | CSL_MEMPROT_L1D_REGS (0x00F00000u) |
| Base address of DMC memory protection registers. More... | |
| #define | CSL_INTC_EVENTID_EVT0 (0) |
| #define | CSL_INTC_EVENTID_EVT1 (1) |
| #define | CSL_INTC_EVENTID_EVT2 (2) |
| #define | CSL_INTC_EVENTID_EVT3 (3) |
| #define | CSL_INTC_EVENTID_T64P0_TINT12 (4) |
| #define | CSL_INTC_EVENTID_BOOTCFGINT0 (5) |
| #define | CSL_INTC_EVENTID_EHRPWM0 (7) |
| #define | CSL_INTC_EVENTID_EDMA3CC_INT1 (8) |
| #define | CSL_INTC_EVENTID_EMU_DTDMA (9) |
| #define | CSL_INTC_EVENTID_EHRPWM0TZ (10) |
| #define | CSL_INTC_EVENTID_EMU_RTDXRX (11) |
| #define | CSL_INTC_EVENTID_EMU_RTDXTX (12) |
| #define | CSL_INTC_EVENTID_IDMA0 (13) |
| #define | CSL_INTC_EVENTID_IDMA1 (14) |
| #define | CSL_INTC_EVENTID_MMCSD0_INT0 (15) |
| #define | CSL_INTC_EVENTID_MMCSD0_INT1 (16) |
| #define | CSL_INTC_EVENTID_EHRPWM1 (18) |
| #define | CSL_INTC_EVENTID_USBINT0 (19) |
| #define | CSL_INTC_EVENTID_USB1_HCINT (20) |
| #define | CSL_INTC_EVENTID_USB1_RWAKEUP (21) |
| #define | CSL_INTC_EVENTID_EHRPWM1TZ (23) |
| #define | CSL_INTC_EVENTID_SATAINT (24) |
| #define | CSL_INTC_EVENTID_T64P2_TINTALL (25) |
| #define | CSL_INTC_EVENTID_EMAC_RXTHRHC0 (26) |
| #define | CSL_INTC_EVENTID_EMAC_RXC0 (27) |
| #define | CSL_INTC_EVENTID_EMAC_TXC0 (28) |
| #define | CSL_INTC_EVENTID_EMAC_MISCC0 (29) |
| #define | CSL_INTC_EVENTID_EMAC_RXTHRHC1 (30) |
| #define | CSL_INTC_EVENTID_EMAC_RXC1 (31) |
| #define | CSL_INTC_EVENTID_EMAC_TXC1 (32) |
| #define | CSL_INTC_EVENTID_EMAC_MISCC1 (33) |
| #define | CSL_INTC_EVENTID_UHPI_DSPINT (34) |
| #define | CSL_INTC_EVENTID_I2CINT0 (36) |
| #define | CSL_INTC_EVENTID_SPIINT0 (37) |
| #define | CSL_INTC_EVENTID_UARTINT0 (38) |
| #define | CSL_INTC_EVENTID_T64P1_TINT12 (40) |
| #define | CSL_INTC_EVENTID_GPIO_BNK1_INT (41) |
| #define | CSL_INTC_EVENTID_I2CINT1 (42) |
| #define | CSL_INTC_EVENTID_SPIINT1 (43) |
| #define | CSL_INTC_EVENTID_ECAPINT0 (45) |
| #define | CSL_INTC_EVENTID_UARTINT1 (46) |
| #define | CSL_INTC_EVENTID_ECAPINT1 (47) |
| #define | CSL_INTC_EVENTID_T64P1_TINT34 (48) |
| #define | CSL_INTC_EVENTID_GPIO_BNK2_INT (49) |
| #define | CSL_INTC_EVENTID_ECAPINT2 (51) |
| #define | CSL_INTC_EVENTID_GPIO_BNK3_INT (52) |
| #define | CSL_INTC_EVENTID_MMCSD1_INT1 (53) |
| #define | CSL_INTC_EVENTID_GPIO_BNK4_INT (54) |
| #define | CSL_INTC_EVENTID_EMIFAINT (55) |
| #define | CSL_INTC_EVENTID_TPCC0_ERRINT (56) |
| #define | CSL_INTC_EVENTID_TPTC_ERRINT0 (57) |
| #define | CSL_INTC_EVENTID_TPTC_ERRINT1 (58) |
| #define | CSL_INTC_EVENTID_GPIO_BNK5_INT (59) |
| #define | CSL_INTC_EVENTID_DDR2_MEMERR (60) |
| #define | CSL_INTC_EVENTID_MCASP0INT (61) |
| #define | CSL_INTC_EVENTID_GPIO_BNK6_INT (62) |
| #define | CSL_INTC_EVENTID_RTC_IRQS (63) |
| #define | CSL_INTC_EVENTID_T64P0_TINT34 (64) |
| #define | CSL_INTC_EVENTID_GPIO_BNK0_INT (65) |
| #define | CSL_INTC_EVENTID_SYSCFG_CHIPINT3 (67) |
| #define | CSL_INTC_EVENTID_MMCSD1_INT0 (68) |
| #define | CSL_INTC_EVENTID_UARTINT2 (69) |
| #define | CSL_INTC_EVENTID_PSC0_ALLINT (70) |
| #define | CSL_INTC_EVENTID_PSC1_ALLINT (71) |
| #define | CSL_INTC_EVENTID_GPIO_BNK7_INT (72) |
| #define | CSL_INTC_EVENTID_LCDC_INT0 (73) |
| #define | CSL_INTC_EVENTID_PROTERR (74) |
| #define | CSL_INTC_EVENTID_GPIO_BNK8_INT (75) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT0 (78) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT1 (79) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT2 (80) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT3 (81) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT4 (82) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT5 (83) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT6 (84) |
| #define | CSL_INTC_EVENTID_T64P2_CMPINT7 (85) |
| #define | CSL_INTC_EVENTID_T64P3_TINTALL (86) |
| #define | CSL_INTC_EVENTID_MCBSP0_RXINT (87) |
| #define | CSL_INTC_EVENTID_MCBSP0_TXINT (88) |
| #define | CSL_INTC_EVENTID_MCBSP1_RXINT (89) |
| #define | CSL_INTC_EVENTID_MCBSP1_TXINT (90) |
| #define | CSL_INTC_EVENTID_EDMA3CC1_INT1 (91) |
| #define | CSL_INTC_EVENTID_EDMA3CC1_ERRINT (92) |
| #define | CSL_INTC_EVENTID_EDMA3TC2_ERRINT (93) |
| #define | CSL_INTC_EVENTID_UPPINT (94) |
| #define | CSL_INTC_EVENTID_VPIFINT (95) |
| #define | CSL_INTC_EVENTID_INTERR (96) |
| #define | CSL_INTC_EVENTID_EMC_IDMAERR (97) |
| #define | CSL_INTC_EVENTID_PMC_ED (113) |
| #define | CSL_INTC_EVENTID_UMC_ED1 (116) |
| #define | CSL_INTC_EVENTID_UMC_ED2 (117) |
| #define | CSL_INTC_EVENTID_PDC_INT (118) |
| #define | CSL_INTC_EVENTID_SYS_CMPA (119) |
| #define | CSL_INTC_EVENTID_PMC_CMPA (120) |
| #define | CSL_INTC_EVENTID_PMC_DMPA (121) |
| #define | CSL_INTC_EVENTID_DMC_CMPA (122) |
| #define | CSL_INTC_EVENTID_DMC_DMPA (123) |
| #define | CSL_INTC_EVENTID_UMC_CMPA (124) |
| #define | CSL_INTC_EVENTID_UMC_DMPA (125) |
| #define | CSL_INTC_EVENTID_EMC_CMPA (126) |
| #define | CSL_INTC_EVENTID_EMC_BUSERR (127) |
| #define | CSL_EDMA3_NUM_DMACH 32 |
| #define | CSL_EDMA3_NUM_QDMACH 8 |
| #define | CSL_EDMA3_NUM_PARAMSETS 128 |
| #define | CSL_EDMA3_NUM_EVQUE 2 |
| #define | CSL_EDMA3_CHMAPEXIST 0 |
| #define | CSL_EDMA3_NUM_REGIONS 4 |
| #define | CSL_EDMA3_MEMPROTECT 0 |
| #define | CSL_EDMA3_CHA_CNT |
| #define | CSL_EDMA3_CHA_MCASP0_RX 0 |
| #define | CSL_EDMA3_CHA_MCASP0_TX 1 |
| #define | CSL_EDMA3_CHA_MCBSP0_RX 2 |
| #define | CSL_EDMA3_CHA_MCBSP0_TX 3 |
| #define | CSL_EDMA3_CHA_MCBSP1_RX 4 |
| #define | CSL_EDMA3_CHA_MCBSP1_TX 5 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT0 6 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT1 7 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT2 22 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT3 23 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT4 28 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT5 29 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT6 16 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT7 17 |
| #define | CSL_EDMA3_CHA_GPIO_BNKINT8 18 |
| #define | CSL_EDMA3_CHA_UART0_RX 8 |
| #define | CSL_EDMA3_CHA_UART0_TX 9 |
| #define | CSL_EDMA3_CHA_UART1_RX 12 |
| #define | CSL_EDMA3_CHA_UART1_TX 13 |
| #define | CSL_EDMA3_CHA_UART2_RX 30 |
| #define | CSL_EDMA3_CHA_UART2_TX 31 |
| #define | CSL_EDMA3_CHA_TIMER64P0_EVT12 10 |
| #define | CSL_EDMA3_CHA_TIMER64P0_EVT34 11 |
| #define | CSL_EDMA3_CHA_TIMER64P2_EVT12 24 |
| #define | CSL_EDMA3_CHA_TIMER64P2_EVT34 25 |
| #define | CSL_EDMA3_CHA_TIMER64P3_EVT12 26 |
| #define | CSL_EDMA3_CHA_TIMER64P3_EVT34 27 |
| #define | CSL_EDMA3_CHA_SPI0_RX 14 |
| #define | CSL_EDMA3_CHA_SPI0_TX 15 |
| #define | CSL_EDMA3_CHA_SPI1_RX 18 |
| #define | CSL_EDMA3_CHA_SPI1_TX 19 |
| #define | CSL_EDMA3_CHA_MMCSD0_RX 16 |
| #define | CSL_EDMA3_CHA_MMCSD0_TX 17 |
| #define | CSL_EDMA3_CHA_MMCSD1_RX 28 |
| #define | CSL_EDMA3_CHA_MMCSD1_TX 29 |
| #define | CSL_EDMA3_CHA_I2C0_RX 24 |
| #define | CSL_EDMA3_CHA_I2C0_TX 25 |
| #define | CSL_EDMA3_CHA_I2C1_RX 26 |
| #define | CSL_EDMA3_CHA_I2C1_TX 27 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT0 00 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT1 01 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT2 02 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT3 03 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT4 04 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT5 05 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT6 06 |
| #define | CSL_EDMA3_TIMER2_T12CMPEVT7 07 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT0 08 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT1 09 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT2 10 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT3 11 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT4 12 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT5 13 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT6 14 |
| #define | CSL_EDMA3_TIMER3_T12CMPEVT7 15 |
| #define | CSL_EDMA3_QCHA_BASE CSL_EDMA3_NUM_DMACH /* QDMA Channel Base */ |
| #define | CSL_EDMA3_QCHA_0 (CSL_EDMA3_QCHA_BASE + 0) /* QDMA Channel 0 */ |
| #define | CSL_EDMA3_QCHA_1 (CSL_EDMA3_QCHA_BASE + 1) /* QDMA Channel 1 */ |
| #define | CSL_EDMA3_QCHA_2 (CSL_EDMA3_QCHA_BASE + 2) /* QDMA Channel 2 */ |
| #define | CSL_EDMA3_QCHA_3 (CSL_EDMA3_QCHA_BASE + 3) /* QDMA Channel 3 */ |
| #define | CSL_EDMA3_QCHA_4 (CSL_EDMA3_QCHA_BASE + 4) /* QDMA Channel 4 */ |
| #define | CSL_EDMA3_QCHA_5 (CSL_EDMA3_QCHA_BASE + 5) /* QDMA Channel 5 */ |
| #define | CSL_EDMA3_QCHA_6 (CSL_EDMA3_QCHA_BASE + 6) /* QDMA Channel 6 */ |
| #define | CSL_EDMA3_QCHA_7 (CSL_EDMA3_QCHA_BASE + 7) /* QDMA Channel 7 */ |
| #define | CSL_EDMA3_REGION_GLOBAL -1 |
| #define | CSL_EDMA3_REGION_0 0 |
| #define | CSL_EDMA3_REGION_1 1 |
| #define | CSL_EDMA3_REGION_2 2 |
| #define | CSL_EDMA3_REGION_3 3 |
| #define | CSL_DAT_QCHA_0 0 |
| Number of Generic Channel instances. More... | |
| #define | CSL_DAT_QCHA_1 1 |
| #define | CSL_DAT_QCHA_2 2 |
| #define | CSL_DAT_QCHA_3 3 |
| #define | CSL_DAT_QCHA_4 4 |
| #define | CSL_DAT_QCHA_5 5 |
| #define | CSL_DAT_QCHA_6 6 |
| #define | CSL_DAT_QCHA_7 7 |
| #define | CSL_DAT_REGION_GLOBAL -1 /* Global Region */ |
| Enumeration for EDMA Regions. More... | |
| #define | CSL_DAT_REGION_0 0 /* EDMA Region 0 */ |
| #define | CSL_DAT_REGION_1 1 /* EDMA Region 1 */ |
| #define | CSL_DAT_REGION_2 2 /* EDMA Region 2 */ |
| #define | CSL_DAT_REGION_3 3 /* EDMA Region 3 */ |
Enumerations | |
| enum | CSL_EdmaccNum { CSL_EDMACC_ANY = -1, CSL_EDMACC_0 = 0 } |
| enum | CSL_Edma3Que { CSL_EDMA3_QUE_0 = 0, CSL_EDMA3_QUE_1 = 1 } |
| enum | CSL_EdmatcNum { CSL_EDMATC_ANY = -1, CSL_EDMATC_0 = 0, CSL_EDMATC_1 = 1 } |
| enum | CSL_DatPriority { CSL_DAT_PRI_DEFAULT = 0, CSL_DAT_PRI_0 = 0, CSL_DAT_PRI_1 = 1 } |
| Enumerations for EDMA Event Queues. More... | |
| #define CSL_AINTC (0) |
Peripheral Instance of AINTC instances.
Definition at line 214 of file soc_OMAPL138.h.
| #define CSL_AINTC_0_REGS (0xFFFEE000u) |
Base address of AINTC memory mapped registers.
Definition at line 406 of file soc_OMAPL138.h.
| #define CSL_AINTC_PER_CNT 1 |
Number of AINTC instances.
Definition at line 116 of file soc_OMAPL138.h.
| #define CSL_CACHE_0_REGS (0x01840000u) |
#brief Cache Module memory mapped address
Definition at line 251 of file soc_OMAPL138.h.
| #define CSL_CPGMACSSR_PER_CNT 1 |
Number of CPGMAC instances.
Definition at line 101 of file soc_OMAPL138.h.
| #define CSL_CPPI_PER_CNT 1 |
Number of CPPI instances.
Definition at line 104 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_0 0 |
Number of Generic Channel instances.
Enumerations for EDMA channels
There are 8 QDMA channels -QDMA Channel 0
Definition at line 865 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_1 1 |
QDMA Channel 1
Definition at line 866 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_2 2 |
QDMA Channel 2
Definition at line 867 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_3 3 |
QDMA Channel 3
Definition at line 868 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_4 4 |
QDMA Channel 4
Definition at line 869 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_5 5 |
QDMA Channel 5
Definition at line 870 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_6 6 |
QDMA Channel 6
Definition at line 871 of file soc_OMAPL138.h.
| #define CSL_DAT_QCHA_7 7 |
QDMA Channel 7
Definition at line 872 of file soc_OMAPL138.h.
| #define CSL_DAT_REGION_0 0 /* EDMA Region 0 */ |
Definition at line 892 of file soc_OMAPL138.h.
| #define CSL_DAT_REGION_1 1 /* EDMA Region 1 */ |
Definition at line 893 of file soc_OMAPL138.h.
| #define CSL_DAT_REGION_2 2 /* EDMA Region 2 */ |
Definition at line 894 of file soc_OMAPL138.h.
| #define CSL_DAT_REGION_3 3 /* EDMA Region 3 */ |
Definition at line 895 of file soc_OMAPL138.h.
| #define CSL_DAT_REGION_GLOBAL -1 /* Global Region */ |
Enumeration for EDMA Regions.
Definition at line 891 of file soc_OMAPL138.h.
| #define CSL_DDR2_0_CTRL_REGS (0xB0000000u) |
Base address of DDR memory mapped registers.
Definition at line 402 of file soc_OMAPL138.h.
| #define CSL_DDR2_0_DATA_REGS (0xC0000000u) |
Definition at line 403 of file soc_OMAPL138.h.
| #define CSL_ECAP_0 (0) |
Peripheral Instance of ECAP instances.
Definition at line 195 of file soc_OMAPL138.h.
| #define CSL_ECAP_0_REGS (0x01F06000u) |
Base address of ECAP memory mapped registers.
Definition at line 372 of file soc_OMAPL138.h.
| #define CSL_ECAP_1 (1) |
Definition at line 196 of file soc_OMAPL138.h.
| #define CSL_ECAP_1_REGS (0x01F07000u) |
Definition at line 373 of file soc_OMAPL138.h.
| #define CSL_ECAP_2 (2) |
Definition at line 197 of file soc_OMAPL138.h.
| #define CSL_ECAP_2_REGS (0x01F08000u) |
Definition at line 374 of file soc_OMAPL138.h.
| #define CSL_ECAP_PER_CNT 3 |
Number of ECAP instances.
Definition at line 98 of file soc_OMAPL138.h.
| #define CSL_ECTL (0) |
Peripheral Instance of ECTL instances.
Definition at line 223 of file soc_OMAPL138.h.
| #define CSL_EDMA30CC_0_REGS (0x01C00000u) |
Base address of Channel controller memory mapped registers.
Definition at line 254 of file soc_OMAPL138.h.
| #define CSL_EDMA30TC_0_REGS (0x01C08000u) |
Base address of Transfer controller memory mapped registers.
Definition at line 257 of file soc_OMAPL138.h.
| #define CSL_EDMA30TC_1_REGS (0x01C08400u) |
Definition at line 258 of file soc_OMAPL138.h.
| #define CSL_EDMA31CC_0_REGS (0x01E30000u) |
Base address of Channel controller memory mapped registers.
Definition at line 358 of file soc_OMAPL138.h.
| #define CSL_EDMA31TC_0_REGS (0x01E38000u) |
Base address of Transfer controller memory mapped registers.
Definition at line 361 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_CNT |
Definition at line 680 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT0 6 |
Definition at line 699 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT1 7 |
Definition at line 701 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT2 22 |
Definition at line 703 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT3 23 |
Definition at line 705 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT4 28 |
Definition at line 707 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT5 29 |
Definition at line 709 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT6 16 |
Definition at line 711 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT7 17 |
Definition at line 713 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_GPIO_BNKINT8 18 |
Definition at line 715 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_I2C0_RX 24 |
Definition at line 765 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_I2C0_TX 25 |
Definition at line 767 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_I2C1_RX 26 |
Definition at line 769 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_I2C1_TX 27 |
Definition at line 771 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCASP0_RX 0 |
Definition at line 686 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCASP0_TX 1 |
Definition at line 688 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCBSP0_RX 2 |
Definition at line 690 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCBSP0_TX 3 |
Definition at line 692 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCBSP1_RX 4 |
Definition at line 694 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MCBSP1_TX 5 |
Definition at line 696 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MMCSD0_RX 16 |
Definition at line 755 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MMCSD0_TX 17 |
Definition at line 757 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MMCSD1_RX 28 |
Definition at line 760 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_MMCSD1_TX 29 |
Definition at line 762 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_SPI0_RX 14 |
Definition at line 746 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_SPI0_TX 15 |
Definition at line 748 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_SPI1_RX 18 |
Definition at line 750 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_SPI1_TX 19 |
Definition at line 752 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P0_EVT12 10 |
Definition at line 731 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P0_EVT34 11 |
Definition at line 733 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P2_EVT12 24 |
Definition at line 736 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P2_EVT34 25 |
Definition at line 738 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P3_EVT12 26 |
Definition at line 741 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_TIMER64P3_EVT34 27 |
Definition at line 743 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART0_RX 8 |
Definition at line 718 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART0_TX 9 |
Definition at line 720 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART1_RX 12 |
Definition at line 722 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART1_TX 13 |
Definition at line 724 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART2_RX 30 |
Definition at line 726 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHA_UART2_TX 31 |
Definition at line 728 of file soc_OMAPL138.h.
| #define CSL_EDMA3_CHMAPEXIST 0 |
Definition at line 673 of file soc_OMAPL138.h.
| #define CSL_EDMA3_MEMPROTECT 0 |
Definition at line 675 of file soc_OMAPL138.h.
| #define CSL_EDMA3_NUM_DMACH 32 |
Definition at line 669 of file soc_OMAPL138.h.
| #define CSL_EDMA3_NUM_EVQUE 2 |
Definition at line 672 of file soc_OMAPL138.h.
| #define CSL_EDMA3_NUM_PARAMSETS 128 |
Definition at line 671 of file soc_OMAPL138.h.
| #define CSL_EDMA3_NUM_QDMACH 8 |
Definition at line 670 of file soc_OMAPL138.h.
| #define CSL_EDMA3_NUM_REGIONS 4 |
Definition at line 674 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_0 (CSL_EDMA3_QCHA_BASE + 0) /* QDMA Channel 0 */ |
Definition at line 809 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_1 (CSL_EDMA3_QCHA_BASE + 1) /* QDMA Channel 1 */ |
Definition at line 810 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_2 (CSL_EDMA3_QCHA_BASE + 2) /* QDMA Channel 2 */ |
Definition at line 811 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_3 (CSL_EDMA3_QCHA_BASE + 3) /* QDMA Channel 3 */ |
Definition at line 812 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_4 (CSL_EDMA3_QCHA_BASE + 4) /* QDMA Channel 4 */ |
Definition at line 813 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_5 (CSL_EDMA3_QCHA_BASE + 5) /* QDMA Channel 5 */ |
Definition at line 814 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_6 (CSL_EDMA3_QCHA_BASE + 6) /* QDMA Channel 6 */ |
Definition at line 815 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_7 (CSL_EDMA3_QCHA_BASE + 7) /* QDMA Channel 7 */ |
Definition at line 816 of file soc_OMAPL138.h.
| #define CSL_EDMA3_QCHA_BASE CSL_EDMA3_NUM_DMACH /* QDMA Channel Base */ |
Definition at line 808 of file soc_OMAPL138.h.
| #define CSL_EDMA3_REGION_0 0 |
Definition at line 843 of file soc_OMAPL138.h.
| #define CSL_EDMA3_REGION_1 1 |
Definition at line 844 of file soc_OMAPL138.h.
| #define CSL_EDMA3_REGION_2 2 |
Definition at line 845 of file soc_OMAPL138.h.
| #define CSL_EDMA3_REGION_3 3 |
Definition at line 846 of file soc_OMAPL138.h.
| #define CSL_EDMA3_REGION_GLOBAL -1 |
Definition at line 842 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT0 00 |
Definition at line 774 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT1 01 |
Definition at line 776 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT2 02 |
Definition at line 778 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT3 03 |
Definition at line 780 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT4 04 |
Definition at line 782 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT5 05 |
Definition at line 784 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT6 06 |
Definition at line 786 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER2_T12CMPEVT7 07 |
Definition at line 788 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT0 08 |
Definition at line 791 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT1 09 |
Definition at line 793 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT2 10 |
Definition at line 795 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT3 11 |
Definition at line 797 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT4 12 |
Definition at line 799 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT5 13 |
Definition at line 801 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT6 14 |
Definition at line 803 of file soc_OMAPL138.h.
| #define CSL_EDMA3_TIMER3_T12CMPEVT7 15 |
Definition at line 805 of file soc_OMAPL138.h.
| #define CSL_EDMA3CC_0 (0) |
Peripheral Instance of EDMA CC instances.
Definition at line 140 of file soc_OMAPL138.h.
| #define CSL_EDMA3CC_1 (1) |
Definition at line 141 of file soc_OMAPL138.h.
| #define CSL_EDMA3CC_CNT 2 |
Number of EDMA3 CC instances.
Definition at line 77 of file soc_OMAPL138.h.
| #define CSL_EDMA3TC_0 (0) |
Peripheral Instance of EDMA TC instances.
Definition at line 144 of file soc_OMAPL138.h.
| #define CSL_EDMA3TC_1 (1) |
Definition at line 145 of file soc_OMAPL138.h.
| #define CSL_EDMA3TC_CNT 3 |
Number of EDMA3 TC instances.
Definition at line 80 of file soc_OMAPL138.h.
| #define CSL_EHRPWM_0 (0) |
Peripheral Instance of EHRPWM instances.
Definition at line 191 of file soc_OMAPL138.h.
| #define CSL_EHRPWM_0_REGS (0x01F00000u) |
Base address of EPWM memory mapped registers.
Definition at line 364 of file soc_OMAPL138.h.
| #define CSL_EHRPWM_1 (1) |
Definition at line 192 of file soc_OMAPL138.h.
| #define CSL_EHRPWM_1_REGS (0x01F02000u) |
Definition at line 365 of file soc_OMAPL138.h.
| #define CSL_EHRPWM_PER_CNT 2 |
Number of EHRPWM instances.
Definition at line 95 of file soc_OMAPL138.h.
| #define CSL_EMAC (0) |
Peripheral Instance of EMAC instances.
Definition at line 185 of file soc_OMAPL138.h.
| #define CSL_EMAC_DSC_CONTROL_REG (0x01E23000u) |
Definition at line 335 of file soc_OMAPL138.h.
| #define CSL_EMAC_DSC_CTRL_MOD_RAM (0x01E20000u) |
Base address of EMAC memory.
Definition at line 333 of file soc_OMAPL138.h.
| #define CSL_EMAC_DSC_CTRL_MOD_REG (0x01E22000u) |
Definition at line 334 of file soc_OMAPL138.h.
| #define CSL_EMAC_PER_CNT 1 |
Number of EMAC instances.
Definition at line 89 of file soc_OMAPL138.h.
| #define CSL_EMC_0_REGS (0x01820000u) |
#brief EMC Module memory mapped address
Definition at line 248 of file soc_OMAPL138.h.
| #define CSL_EMIFA (0) |
Peripheral Instance of EMIFA instances.
Definition at line 182 of file soc_OMAPL138.h.
| #define CSL_EMIFA_0_REGS (0x68000000u) |
Base address of EMIFA memory mapped registers.
Definition at line 384 of file soc_OMAPL138.h.
| #define CSL_EMIFA_CS0_ADDR (0x40000000u) |
Base address of EMIFA_CS0 memory.
Definition at line 387 of file soc_OMAPL138.h.
| #define CSL_EMIFA_CS2_ADDR (0x60000000u) |
Base address of EMIFA_CS2 memory.
Definition at line 390 of file soc_OMAPL138.h.
| #define CSL_EMIFA_CS3_ADDR (0x62000000u) |
Base address of EMIFA_CS3 memory.
Definition at line 393 of file soc_OMAPL138.h.
| #define CSL_EMIFA_CS4_ADDR (0x64000000u) |
Base address of EMIFA_CS4 memory.
Definition at line 396 of file soc_OMAPL138.h.
| #define CSL_EMIFA_CS5_ADDR (0x66000000u) |
Base address of EMIFA_CS5 memory.
Definition at line 399 of file soc_OMAPL138.h.
| #define CSL_EMIFA_PER_CNT 1 |
Number of EMIFA instances.
Definition at line 83 of file soc_OMAPL138.h.
| #define CSL_EMIFB_PER_CNT 1 |
Number of EMIFB instances.
Definition at line 86 of file soc_OMAPL138.h.
| #define CSL_GPIO (0) |
Peripheral Instance of GPIO instances.
Definition at line 220 of file soc_OMAPL138.h.
| #define CSL_GPIO_0_REGS (0x01E26000u) |
Base address of GPIO memory mapped registers.
Definition at line 346 of file soc_OMAPL138.h.
| #define CSL_GPIO_PER_CNT 1 |
Number of GPIO instances.
Definition at line 125 of file soc_OMAPL138.h.
| #define CSL_HPI (0) |
Peripheral Instances of UHPI instances.
Definition at line 134 of file soc_OMAPL138.h.
| #define CSL_HPI_0_REGS (0x01E10000u) |
Base address of HPI memory mapped registers.
Definition at line 312 of file soc_OMAPL138.h.
| #define CSL_HPI_PER_CNT 1 |
Number of UHPI instances.
Definition at line 44 of file soc_OMAPL138.h.
| #define CSL_HRPWM_0_REGS (0x01F01000u) |
Base address of EPWM memory mapped registers.
Definition at line 368 of file soc_OMAPL138.h.
| #define CSL_HRPWM_1_REGS (0x01F03000u) |
Definition at line 369 of file soc_OMAPL138.h.
| #define CSL_I2C_0 (0) |
Peripheral Instances of I2C instances.
Definition at line 167 of file soc_OMAPL138.h.
| #define CSL_I2C_0_REGS (0x01C22000u) |
Base address of I2C memory mapped registers.
Definition at line 274 of file soc_OMAPL138.h.
| #define CSL_I2C_1 (1) |
Definition at line 168 of file soc_OMAPL138.h.
| #define CSL_I2C_1_REGS (0x01E28000u) |
Base address of I2C memory mapped registers.
Definition at line 352 of file soc_OMAPL138.h.
| #define CSL_I2C_PER_CNT 2 |
Number of I2C instances.
Definition at line 62 of file soc_OMAPL138.h.
| #define CSL_IDEF_INLINE static inline |
Definition at line 33 of file soc_OMAPL138.h.
| #define CSL_IDMA_0_REGS (0x01820000u) |
#brief IDMA Module memory mapped address
Definition at line 245 of file soc_OMAPL138.h.
| #define CSL_INTC (0) |
Peripheral Instance of INTC instances.
Definition at line 211 of file soc_OMAPL138.h.
| #define CSL_INTC_0_REGS (0x01800000u) |
Base address of INTC memory mapped registers.
Definition at line 233 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_BOOTCFGINT0 (5) |
Definition at line 437 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_DDR2_MEMERR (60) |
Definition at line 552 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_DMC_CMPA (122) |
Definition at line 650 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_DMC_DMPA (123) |
Definition at line 652 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_ECAPINT0 (45) |
Definition at line 513 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_ECAPINT1 (47) |
Definition at line 519 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_ECAPINT2 (51) |
Definition at line 528 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EDMA3CC1_ERRINT (92) |
Definition at line 618 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EDMA3CC1_INT1 (91) |
Definition at line 615 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EDMA3CC_INT1 (8) |
Definition at line 442 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EDMA3TC2_ERRINT (93) |
Definition at line 621 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EHRPWM0 (7) |
Definition at line 439 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EHRPWM0TZ (10) |
Definition at line 447 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EHRPWM1 (18) |
Definition at line 464 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EHRPWM1TZ (23) |
Definition at line 471 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_MISCC0 (29) |
Definition at line 483 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_MISCC1 (33) |
Definition at line 487 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_RXC0 (27) |
Definition at line 481 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_RXC1 (31) |
Definition at line 485 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_RXTHRHC0 (26) |
Definition at line 480 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_RXTHRHC1 (30) |
Definition at line 484 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_TXC0 (28) |
Definition at line 482 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMAC_TXC1 (32) |
Definition at line 486 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMC_BUSERR (127) |
Definition at line 660 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMC_CMPA (126) |
Definition at line 658 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMC_IDMAERR (97) |
Definition at line 630 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMIFAINT (55) |
Definition at line 540 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMU_DTDMA (9) |
Definition at line 444 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMU_RTDXRX (11) |
Definition at line 450 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EMU_RTDXTX (12) |
Definition at line 452 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EVT0 (0) |
Definition at line 425 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EVT1 (1) |
Definition at line 427 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EVT2 (2) |
Definition at line 429 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_EVT3 (3) |
Definition at line 431 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK0_INT (65) |
Definition at line 567 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK1_INT (41) |
Definition at line 505 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK2_INT (49) |
Definition at line 525 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK3_INT (52) |
Definition at line 531 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK4_INT (54) |
Definition at line 537 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK5_INT (59) |
Definition at line 549 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK6_INT (62) |
Definition at line 558 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK7_INT (72) |
Definition at line 582 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_GPIO_BNK8_INT (75) |
Definition at line 591 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_I2CINT0 (36) |
Definition at line 493 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_I2CINT1 (42) |
Definition at line 507 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_IDMA0 (13) |
Definition at line 455 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_IDMA1 (14) |
Definition at line 457 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_INTERR (96) |
Definition at line 628 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_LCDC_INT0 (73) |
Definition at line 585 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MCASP0INT (61) |
Definition at line 555 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MCBSP0_RXINT (87) |
Definition at line 606 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MCBSP0_TXINT (88) |
Definition at line 608 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MCBSP1_RXINT (89) |
Definition at line 610 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MCBSP1_TXINT (90) |
Definition at line 612 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MMCSD0_INT0 (15) |
Definition at line 460 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MMCSD0_INT1 (16) |
Definition at line 462 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MMCSD1_INT0 (68) |
Definition at line 573 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_MMCSD1_INT1 (53) |
Definition at line 534 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PDC_INT (118) |
Definition at line 640 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PMC_CMPA (120) |
Definition at line 646 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PMC_DMPA (121) |
Definition at line 648 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PMC_ED (113) |
Definition at line 633 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PROTERR (74) |
Definition at line 588 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PSC0_ALLINT (70) |
Definition at line 578 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_PSC1_ALLINT (71) |
Definition at line 579 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_RTC_IRQS (63) |
Definition at line 561 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_SATAINT (24) |
Definition at line 474 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_SPIINT0 (37) |
Definition at line 496 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_SPIINT1 (43) |
Definition at line 510 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_SYS_CMPA (119) |
Definition at line 643 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_SYSCFG_CHIPINT3 (67) |
Definition at line 570 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P0_TINT12 (4) |
Definition at line 434 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P0_TINT34 (64) |
Definition at line 564 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P1_TINT12 (40) |
Definition at line 502 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P1_TINT34 (48) |
Definition at line 522 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT0 (78) |
Definition at line 594 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT1 (79) |
Definition at line 595 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT2 (80) |
Definition at line 596 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT3 (81) |
Definition at line 597 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT4 (82) |
Definition at line 598 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT5 (83) |
Definition at line 599 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT6 (84) |
Definition at line 600 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_CMPINT7 (85) |
Definition at line 601 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P2_TINTALL (25) |
Definition at line 477 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_T64P3_TINTALL (86) |
Definition at line 603 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_TPCC0_ERRINT (56) |
Definition at line 543 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_TPTC_ERRINT0 (57) |
Definition at line 545 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_TPTC_ERRINT1 (58) |
Definition at line 546 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UARTINT0 (38) |
Definition at line 499 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UARTINT1 (46) |
Definition at line 516 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UARTINT2 (69) |
Definition at line 576 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UHPI_DSPINT (34) |
Definition at line 490 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UMC_CMPA (124) |
Definition at line 654 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UMC_DMPA (125) |
Definition at line 656 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UMC_ED1 (116) |
Definition at line 636 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UMC_ED2 (117) |
Definition at line 638 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_UPPINT (94) |
Definition at line 624 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_USB1_HCINT (20) |
Definition at line 468 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_USB1_RWAKEUP (21) |
Definition at line 469 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_USBINT0 (19) |
Definition at line 467 of file soc_OMAPL138.h.
| #define CSL_INTC_EVENTID_VPIFINT (95) |
Definition at line 626 of file soc_OMAPL138.h.
| #define CSL_INTC_PER_CNT 1 |
Number of INTC instances.
Definition at line 113 of file soc_OMAPL138.h.
| #define CSL_LCDC (0) |
Peripheral Instances of LCDC instances.
Definition at line 175 of file soc_OMAPL138.h.
| #define CSL_LCDC_0_REGS (0x01E13000u) |
Base address of LCDC memory mapped registers.
Definition at line 315 of file soc_OMAPL138.h.
| #define CSL_LCDC_PER_CNT 1 |
Number of LCDC instances.
Definition at line 71 of file soc_OMAPL138.h.
| #define CSL_MCASP_0 (0) |
Peripheral Instances of McASP instances.
Definition at line 137 of file soc_OMAPL138.h.
| #define CSL_MCASP_0_CTRL_REGS (0x01D00000u) |
Base address of McASP memory mapped registers.
Definition at line 289 of file soc_OMAPL138.h.
| #define CSL_MCASP_0_DATA_REGS (0x01D02000u) |
Definition at line 291 of file soc_OMAPL138.h.
| #define CSL_MCASP_0_FIFO_REGS (0x01D01000u) |
Definition at line 290 of file soc_OMAPL138.h.
| #define CSL_MCASP_PER_CNT 1 |
Number of McASP instances.
Definition at line 47 of file soc_OMAPL138.h.
| #define CSL_MCBSP_0_CTRL_REGS (0x01D10000u) |
Base address of McBSP memory mapped registers.
Definition at line 298 of file soc_OMAPL138.h.
| #define CSL_MCBSP_0_DATA_REGS (0x01F10000u) |
Definition at line 300 of file soc_OMAPL138.h.
| #define CSL_MCBSP_0_FIFO_REGS (0x01D10800u) |
Definition at line 299 of file soc_OMAPL138.h.
| #define CSL_MCBSP_1_CTRL_REGS (0x01D11000u) |
Base address of McASP memory mapped registers.
Definition at line 303 of file soc_OMAPL138.h.
| #define CSL_MCBSP_1_DATA_REGS (0x01F10000u) |
Definition at line 305 of file soc_OMAPL138.h.
| #define CSL_MCBSP_1_FIFO_REGS (0x01D11800u) |
Definition at line 304 of file soc_OMAPL138.h.
| #define CSL_MCBSP_PER_CNT 2 |
Number of Mcbsp instances.
Definition at line 74 of file soc_OMAPL138.h.
| #define CSL_MDIO (0) |
Peripheral Instance of MDIO instances.
Definition at line 188 of file soc_OMAPL138.h.
| #define CSL_MDIO_0_REGS (0x01E24000u) |
Definition at line 336 of file soc_OMAPL138.h.
| #define CSL_MDIO_PER_CNT 1 |
Number of MDIO instances.
Definition at line 92 of file soc_OMAPL138.h.
| #define CSL_MEMPROT_L1D_REGS (0x00F00000u) |
Base address of DMC memory protection registers.
Definition at line 415 of file soc_OMAPL138.h.
| #define CSL_MEMPROT_L1P_REGS (0x00E00000u) |
Base address of PMC memory Protection registers.
Definition at line 412 of file soc_OMAPL138.h.
| #define CSL_MEMPROT_L2_REGS (0x00800000u) |
Base address of UMC Memory protection registers.
Definition at line 409 of file soc_OMAPL138.h.
| #define CSL_MMCSD_0 (0) |
Peripheral Instances of MMCSD instances.
Definition at line 171 of file soc_OMAPL138.h.
| #define CSL_MMCSD_0_REGS (0x01C40000u) |
Base address of MMCSD memory mapped registers.
Definition at line 280 of file soc_OMAPL138.h.
| #define CSL_MMCSD_1 (1) |
Definition at line 172 of file soc_OMAPL138.h.
| #define CSL_MMCSD_1_REGS (0x01E1B000u) |
Base address of MMCSD memory mapped registers.
Definition at line 330 of file soc_OMAPL138.h.
| #define CSL_MMCSD_PER_CNT 2 |
Number of MMCSD instances.
Definition at line 68 of file soc_OMAPL138.h.
| #define CSL_PLLC_0 (0) |
Instance number of PLL controller.
Definition at line 178 of file soc_OMAPL138.h.
| #define CSL_PLLC_0_REGS (0x01C11000u) |
PLL controller instance o module address.
Definition at line 264 of file soc_OMAPL138.h.
| #define CSL_PLLC_1 (1) |
Definition at line 179 of file soc_OMAPL138.h.
| #define CSL_PLLC_1_REGS (0X01E1A000u) |
PLL controller instance 1 module address.
Definition at line 327 of file soc_OMAPL138.h.
| #define CSL_PLLC_PER_CNT 2 |
Number of PLL instances.
Definition at line 65 of file soc_OMAPL138.h.
| #define CSL_PRUCORE_0 (0) |
Peripheral Instance of PRU CORE instances.
Definition at line 204 of file soc_OMAPL138.h.
| #define CSL_PRUCORE_0_REGS (0x01C37000u) |
Base address of PRU Core Regsiters.
Definition at line 339 of file soc_OMAPL138.h.
| #define CSL_PRUCORE_1 (1) |
Definition at line 205 of file soc_OMAPL138.h.
| #define CSL_PRUCORE_1_REGS (0x01C37800u) |
Definition at line 340 of file soc_OMAPL138.h.
| #define CSL_PRUINTC (0) |
Peripheral Instance of PRUINTC instances.
Definition at line 208 of file soc_OMAPL138.h.
| #define CSL_PRUINTC_0_REGS (0x01C34000u) |
Base address of PRU Interrupt Controller Registers.
Definition at line 343 of file soc_OMAPL138.h.
| #define CSL_PSC_0 (0) |
Peripheral Instances of PSC instances.
Definition at line 154 of file soc_OMAPL138.h.
| #define CSL_PSC_0_REGS (0x01C10000u) |
Base address of PSC memory mapped registers.
Definition at line 261 of file soc_OMAPL138.h.
| #define CSL_PSC_1 (1) |
Definition at line 155 of file soc_OMAPL138.h.
| #define CSL_PSC_1_REGS (0x01E27000u) |
Base address of PSC memory mapped registers.
Definition at line 349 of file soc_OMAPL138.h.
| #define CSL_PSC_PER_CNT 2 |
Number of PSC instances.
Definition at line 53 of file soc_OMAPL138.h.
| #define CSL_PWRDWN_PDC_REGS (0x01810000u) |
Base address of PDC memory mapped registers.
Definition at line 236 of file soc_OMAPL138.h.
| #define CSL_RTC (0) |
Peripheral Instance of RTC instances.
Definition at line 217 of file soc_OMAPL138.h.
| #define CSL_RTC_0_REGS (0x01C23000u) |
Base address of RTC memory.
Definition at line 277 of file soc_OMAPL138.h.
| #define CSL_RTC_PER_CNT 1 |
Number of RTC instances.
Definition at line 122 of file soc_OMAPL138.h.
| #define CSL_SATA_0_REGS (0x01E18000u) |
Base address of SATA memory mapped registers.
Definition at line 324 of file soc_OMAPL138.h.
| #define CSL_SATA_PER_CNT 1 |
Number of SATA instances.
Definition at line 119 of file soc_OMAPL138.h.
| #define CSL_SPI_0 (0) |
Peripheral Instances of SPI instances.
Definition at line 163 of file soc_OMAPL138.h.
| #define CSL_SPI_0_REGS (0x01C41000u) |
Base address of SPI memory mapped registers.
Definition at line 283 of file soc_OMAPL138.h.
| #define CSL_SPI_1 (1) |
Definition at line 164 of file soc_OMAPL138.h.
| #define CSL_SPI_1_REGS (0x01F0E000u) |
Base address of SPI memory mapped registers.
Definition at line 381 of file soc_OMAPL138.h.
| #define CSL_SPI_PER_CNT 2 |
Number of SPI instances.
Definition at line 59 of file soc_OMAPL138.h.
| #define CSL_SYS_0_REV_ID_REGS (0x01812000u) |
Base address of SYS - Revision ID register.
Definition at line 242 of file soc_OMAPL138.h.
| #define CSL_SYS_0_SECURITY_ID_REGS (0x01811000u) |
Base address of SYS - Security ID register.
Definition at line 239 of file soc_OMAPL138.h.
| #define CSL_SYSCFG (2) |
Peripheral Instance of SYSCFG instances.
Definition at line 226 of file soc_OMAPL138.h.
| #define CSL_SYSCFG_0_REGS (0x01C14000u) |
Base address of DEV memory mapped registers.
Definition at line 267 of file soc_OMAPL138.h.
| #define CSL_SYSCFG_1_REGS (0x01E2C000u) |
Base address of syscfg registers.
Definition at line 355 of file soc_OMAPL138.h.
| #define CSL_SYSCFG_PER_CNT 2 |
Number of SYSCFG instances.
Definition at line 128 of file soc_OMAPL138.h.
| #define CSL_TMR_0 (0) |
Peripheral Instance of Timer 64 instances.
Definition at line 148 of file soc_OMAPL138.h.
| #define CSL_TMR_0_REGS (0x01C20000u) |
Base address of TIMER memory mapped registers.
Definition at line 270 of file soc_OMAPL138.h.
| #define CSL_TMR_1 (1) |
Definition at line 149 of file soc_OMAPL138.h.
| #define CSL_TMR_1_REGS (0x01C21000u) |
Definition at line 271 of file soc_OMAPL138.h.
| #define CSL_TMR_2 (2) |
Definition at line 150 of file soc_OMAPL138.h.
| #define CSL_TMR_2_REGS (0x01F0C000u) |
Base address of TIMER memory mapped registers.
Definition at line 377 of file soc_OMAPL138.h.
| #define CSL_TMR_3 (3) |
Definition at line 151 of file soc_OMAPL138.h.
| #define CSL_TMR_3_REGS (0x01F0D000u) |
Definition at line 378 of file soc_OMAPL138.h.
| #define CSL_TMR_PER_CNT 4 |
Number of TIMER instances.
Definition at line 50 of file soc_OMAPL138.h.
| #define CSL_UART_0 (0) |
Peripheral Instances of UART instances.
Definition at line 158 of file soc_OMAPL138.h.
| #define CSL_UART_0_REGS (0x01C42000u) |
Base address of UART memory mapped registers.
Definition at line 286 of file soc_OMAPL138.h.
| #define CSL_UART_1 (1) |
Definition at line 159 of file soc_OMAPL138.h.
| #define CSL_UART_1_REGS (0x01D0C000u) |
Base address of UART memory mapped registers.
Definition at line 294 of file soc_OMAPL138.h.
| #define CSL_UART_2 (2) |
Definition at line 160 of file soc_OMAPL138.h.
| #define CSL_UART_2_REGS (0x01D0D000u) |
Definition at line 295 of file soc_OMAPL138.h.
| #define CSL_UART_PER_CNT 3 |
Number of UART instances.
Definition at line 56 of file soc_OMAPL138.h.
| #define CSL_UPP_0_REGS (0x01E16000u) |
Base address of UPP memory mapped registers.
Definition at line 318 of file soc_OMAPL138.h.
| #define CSL_UPP_PER_CNT 1 |
Number of UPP instances.
Definition at line 41 of file soc_OMAPL138.h.
| #define CSL_USB_0 (0) |
Peripheral Instance of USB instances.
Definition at line 200 of file soc_OMAPL138.h.
| #define CSL_USB_0_REGS (0x01E00000u) |
Base address of USB memory.
Definition at line 308 of file soc_OMAPL138.h.
| #define CSL_USB_1 (1) |
Definition at line 201 of file soc_OMAPL138.h.
| #define CSL_USB_1_REGS (0x01E25000u) |
Definition at line 309 of file soc_OMAPL138.h.
| #define CSL_USB_PER_CNT 2 |
Number of USB instances.
Definition at line 107 of file soc_OMAPL138.h.
| #define CSL_VPIF_0_REGS (0x01E17000u) |
Base address of VPIF memory mapped registers.
Definition at line 321 of file soc_OMAPL138.h.
| #define CSL_VPIF_PER_CNT 1 |
Number of VPIF instances.
Definition at line 110 of file soc_OMAPL138.h.
| enum CSL_DatPriority |
Enumerations for EDMA Event Queues.
There are two Event Queues. Q0 is the highest priority and Q1 is the least priority
| Enumerator | |
|---|---|
| CSL_DAT_PRI_DEFAULT | |
| CSL_DAT_PRI_0 | |
| CSL_DAT_PRI_1 | |
Definition at line 880 of file soc_OMAPL138.h.
| enum CSL_Edma3Que |
| Enumerator | |
|---|---|
| CSL_EDMA3_QUE_0 | |
| CSL_EDMA3_QUE_1 | |
Definition at line 825 of file soc_OMAPL138.h.
| enum CSL_EdmaccNum |
| Enumerator | |
|---|---|
| CSL_EDMACC_ANY | |
| CSL_EDMACC_0 | |
Definition at line 819 of file soc_OMAPL138.h.
| enum CSL_EdmatcNum |
| Enumerator | |
|---|---|
| CSL_EDMATC_ANY | |
| CSL_EDMATC_0 | |
| CSL_EDMATC_1 | |
Definition at line 836 of file soc_OMAPL138.h.
1.8.7