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suart_api.c
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1 /*
2  * pru/hal/uart/src/suart_api.c
3  *
4  * Copyright (C) 2010 Texas Instruments Incorporated
5  * Author: Jitendra Kumar <jitendra@mistralsolutions.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
12  * whether express or implied; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14  * General Public License for more details.
15  */
16 
17 /*
18  *====================
19  * Includes
20  *====================
21  */
22 
23 #include "suart_api.h"
24 #include "suart_pru_regs.h"
25 #include "pru.h"
26 #include "omapl_suart_board.h"
27 #include "suart_utils.h"
28 #include "suart_err.h"
29 
30 #include "csl/cslr_mcasp.h"
31 
32 static unsigned char gUartStatuTable[8];
33 static arm_pru_iomap pru_arm_iomap;
34 static int suart_set_pru_id (unsigned int pru_no);
35 static void pru_set_rx_tx_mode(Uint32 pru_mode, Uint32 pruNum);
36 static void pru_set_delay_count (Uint32 pru_freq);
37 
38 #if (PRU_ACTIVE == BOTH_PRU)
39 void pru_set_ram_data (arm_pru_iomap * arm_iomap_pru)
40 {
41 
42  PRU_SUART_RegsOvly pru_suart_regs = (PRU_SUART_RegsOvly) arm_iomap_pru->pru_io_addr;
43  unsigned int * pu32SrCtlAddr = (unsigned int *) ((unsigned int)
44  arm_iomap_pru->mcasp_io_addr + 0x180);
45  pru_suart_tx_cntx_priv * pru_suart_tx_priv = NULL;
46  pru_suart_rx_cntx_priv * pru_suart_rx_priv = NULL;
47  unsigned char * pu32_pru_ram_base = (unsigned char *) arm_iomap_pru->pru_io_addr;
48 
49  /* ***************************** RX PRU - 0 **************************************** */
50 
51  /* Chanel 0 context information */
52  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
53  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART1_CONFIG_RX_SER);
54  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
55  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
56 #if ((PRU_SUART1_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
57  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
58 #else
59  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
60  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART1_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
61 #endif
62  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
63  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
64  pru_suart_regs->Reserved1 = 0;
65  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x090); /* SUART1 RX context base addr */
66  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART1_CONFIG_RX_SER << 2));
67  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART1_CONFIG_RX_SER << 2));
68 
69  /* Chanel 1 context information */
70  pru_suart_regs++;
71  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
72  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART2_CONFIG_RX_SER);
73  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
74  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
75 #if ((PRU_SUART2_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
76  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
77 #else
78  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
79  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART2_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
80 #endif
81  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
82  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
83  pru_suart_regs->Reserved1 = 0;
84  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x0B0); /* SUART2 RX context base addr */
85  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART2_CONFIG_RX_SER << 2));
86  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART2_CONFIG_RX_SER << 2));
87 
88  /* Chanel 2 context information */
89  pru_suart_regs++;
90  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
91  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART3_CONFIG_RX_SER);
92  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
93  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
94 #if ((PRU_SUART3_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
95  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
96 #else
97  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
98  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART3_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
99 #endif
100  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
101  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
102  pru_suart_regs->Reserved1 = 0;
103  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x0D0); /* SUART3 RX context base addr */
104  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART3_CONFIG_RX_SER << 2));
105  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART3_CONFIG_RX_SER << 2));
106 
107  /* Chanel 3 context information */
108  pru_suart_regs++;
109  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
110  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART4_CONFIG_RX_SER);
111  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
112  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
113 #if ((PRU_SUART4_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
114  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
115 #else
116  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
117  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART4_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
118 #endif
119  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
120  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
121  pru_suart_regs->Reserved1 = 0;
122  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x0F0); /* SUART4 RX context base addr */
123  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART4_CONFIG_RX_SER << 2));
124  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART4_CONFIG_RX_SER << 2));
125 
126  /* Chanel 4 context information */
127  pru_suart_regs++;
128  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
129  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART5_CONFIG_RX_SER);
130  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
131  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
132 #if ((PRU_SUART5_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
133  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
134 #else
135  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
136  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART5_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
137 #endif
138  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
139  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
140  pru_suart_regs->Reserved1 = 0;
141  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x110); /* SUART5 RX context base addr */
142  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART5_CONFIG_RX_SER << 2));
143  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART5_CONFIG_RX_SER << 2));
144 
145  /* Chanel 5 context information */
146  pru_suart_regs++;
147  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
148  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART6_CONFIG_RX_SER);
149  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
150  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
151 #if ((PRU_SUART6_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
152  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
153 #else
154  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
155  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART6_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
156 #endif
157  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
158  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
159  pru_suart_regs->Reserved1 = 0;
160  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x130); /* SUART6 RX context base addr */
161  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART6_CONFIG_RX_SER << 2));
162  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART6_CONFIG_RX_SER << 2));
163 
164  /* Chanel 6 context information */
165  pru_suart_regs++;
166  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
167  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART7_CONFIG_RX_SER);
168  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
169  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
170 #if ((PRU_SUART7_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
171  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
172 #else
173  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
174  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART7_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
175 #endif
176  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
177  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
178  pru_suart_regs->Reserved1 = 0;
179  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x150); /* SUART7 RX context base addr */
180  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART7_CONFIG_RX_SER << 2));
181  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART7_CONFIG_RX_SER << 2));
182 
183  /* Chanel 7 context information */
184  pru_suart_regs++;
185  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
186  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART8_CONFIG_RX_SER);
187  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
188  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
189 #if ((PRU_SUART8_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
190  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
191 #else
192  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
193  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART8_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
194 #endif
195  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
196  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
197  pru_suart_regs->Reserved1 = 0;
198  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x170); /* SUART8 RX context base addr */
199  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART8_CONFIG_RX_SER << 2));
200  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART8_CONFIG_RX_SER << 2));
201 
202 
203  /* ****************************** PRU1 RAM BASE ADDR ******************************** */
204  pru_suart_regs = (PRU_SUART_RegsOvly) ((unsigned int)
205  arm_iomap_pru->pru_io_addr + 0x2000);
206  pu32_pru_ram_base = (unsigned char *) ((unsigned int)
207  arm_iomap_pru->pru_io_addr + 0x2000);
208 
209  /* ***************************** TX PRU - 1 **************************************** */
210  /* Channel 0 context information */
211  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
212  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART1_CONFIG_TX_SER);
213  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
214  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
215 #if ((PRU_SUART1_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
216  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
217 #else
218  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
219  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART1_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
220 #endif
221  pru_suart_regs->Reserved1 = 1;
222 
223  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x0B0); /* SUART1 TX context base addr */
224  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART1_CONFIG_TX_SER << 2));
225  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART1_CONFIG_TX_SER << 2));
226  pru_suart_tx_priv->buff_addr = 0x0090; /* SUART1 TX formatted data base addr */
227 
228  /* Channel 1 context information */
229  pru_suart_regs++;
230  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
231  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART2_CONFIG_TX_SER);
232  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
233  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
234 #if ((PRU_SUART2_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
235  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
236 #else
237  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
238  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART2_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
239 #endif
240  pru_suart_regs->Reserved1 = 1;
241 
242  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x0DC); /* SUART2 TX context base addr */
243  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART2_CONFIG_TX_SER << 2));
244  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART2_CONFIG_TX_SER << 2));
245  pru_suart_tx_priv->buff_addr = 0x00BC; /* SUART2 TX formatted data base addr */
246 
247  /* Channel 2 context information */
248  pru_suart_regs++;
249  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
250  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART3_CONFIG_TX_SER);
251  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
252  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
253 #if ((PRU_SUART3_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
254  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
255 #else
256  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
257  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART3_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
258 #endif
259  pru_suart_regs->Reserved1 = 1;
260 
261  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x108); /* SUART3 TX context base addr */
262  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART3_CONFIG_TX_SER << 2));
263  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART3_CONFIG_TX_SER << 2));
264  pru_suart_tx_priv->buff_addr = 0x00E8; /* SUART3 TX formatted data base addr */
265 
266  /* Channel 3 context information */
267  pru_suart_regs++;
268  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
269  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART4_CONFIG_TX_SER);
270  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
271  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
272 #if ((PRU_SUART4_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
273  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
274 #else
275  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
276  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART4_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
277 #endif
278  pru_suart_regs->Reserved1 = 1;
279 
280  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x134); /* SUART4 TX context base addr */
281  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART4_CONFIG_TX_SER << 2));
282  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART4_CONFIG_TX_SER << 2));
283  pru_suart_tx_priv->buff_addr = 0x0114; /* SUART4 TX formatted data base addr */
284 
285  /* Channel 4 context information */
286  pru_suart_regs++;
287  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
288  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART5_CONFIG_TX_SER);
289  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
290  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
291 #if ((PRU_SUART5_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
292  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
293 #else
294  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
295  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART5_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
296 #endif
297  pru_suart_regs->Reserved1 = 1;
298 
299  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x160); /* SUART5 TX context base addr */
300  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART5_CONFIG_TX_SER << 2));
301  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART5_CONFIG_TX_SER << 2));
302  pru_suart_tx_priv->buff_addr = 0x0140; /* SUART5 TX formatted data base addr */
303 
304  /* Channel 5 context information */
305  pru_suart_regs++;
306  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
307  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART6_CONFIG_TX_SER);
308  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
309  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
310 #if ((PRU_SUART6_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
311  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
312 #else
313  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
314  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART6_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
315 #endif
316  pru_suart_regs->Reserved1 = 1;
317 
318  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x18C); /* SUART6 TX context base addr */
319  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART6_CONFIG_TX_SER << 2));
320  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART6_CONFIG_TX_SER << 2));
321  pru_suart_tx_priv->buff_addr = 0x016C; /* SUART6 TX formatted data base addr */
322 
323  /* Channel 6 context information */
324  pru_suart_regs++;
325  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
326  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART7_CONFIG_TX_SER);
327  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
328  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
329 #if ((PRU_SUART7_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
330  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
331 #else
332  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
333  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART7_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
334 #endif
335  pru_suart_regs->Reserved1 = 1;
336 
337  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x1B8); /* SUART7 TX context base addr */
338  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART7_CONFIG_TX_SER << 2));
339  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART7_CONFIG_TX_SER << 2));
340  pru_suart_tx_priv->buff_addr = 0x0198; /* SUART7 TX formatted data base addr */
341 
342  /* Channel 7 context information */
343  pru_suart_regs++;
344  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
345  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART8_CONFIG_TX_SER);
346  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
347  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
348 #if ((PRU_SUART8_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
349  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
350 #else
351  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
352  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART8_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
353 #endif
354  pru_suart_regs->Reserved1 = 1;
355  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x1E4); /* SUART8 TX context base addr */
356  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART8_CONFIG_TX_SER << 2));
357  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART8_CONFIG_TX_SER << 2));
358  pru_suart_tx_priv->buff_addr = 0x01C4; /* SUART8 TX formatted data base addr */
359 }
360 #else
361 void pru_set_ram_data (arm_pru_iomap * arm_iomap_pru)
362 {
363 
364  PRU_SUART_RegsOvly pru_suart_regs = (PRU_SUART_RegsOvly) arm_iomap_pru->pru_io_addr;
365  unsigned int * pu32SrCtlAddr = (unsigned int *) ((unsigned int)
366  arm_iomap_pru->mcasp_io_addr + 0x180);
367  pru_suart_tx_cntx_priv * pru_suart_tx_priv = NULL;
368  pru_suart_rx_cntx_priv * pru_suart_rx_priv = NULL;
369  unsigned char * pu32_pru_ram_base = (unsigned char *) arm_iomap_pru->pru_io_addr;
370 
371  /* ***************************** UART 0 **************************************** */
372 
373  /* Channel 0 context information is Tx */
374  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
375  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART1_CONFIG_TX_SER);
376  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
377  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
378 #if ((PRU_SUART1_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
379  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
380 #else
381  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
382  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART1_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
383 #endif
384  pru_suart_regs->Reserved1 = 1;
385  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x0B0); /* SUART1 TX context base addr */
386  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)(MCASP_SRCTL_BASE_ADDR + (PRU_SUART1_CONFIG_TX_SER << 2));
387  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART1_CONFIG_TX_SER << 2));
388  pru_suart_tx_priv->buff_addr = 0x0090; /* SUART1 TX formatted data base addr */
389 
390  /* Channel 1 is Rx context information */
391  pru_suart_regs++;
392  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
393  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART1_CONFIG_RX_SER);
394  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
395  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
396 #if ((PRU_SUART1_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
397  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
398 #else
399  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
400  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART1_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
401 #endif
402  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
403  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
404  pru_suart_regs->Reserved1 = 0;
405  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x0C0); /* SUART1 RX context base addr */
406  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART1_CONFIG_RX_SER << 2));
407  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART1_CONFIG_RX_SER << 2));
408 
409 
410  /* ***************************** UART 1 **************************************** */
411  /* Channel 2 context information is Tx */
412  pru_suart_regs++;
413  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
414  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART2_CONFIG_TX_SER);
415  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
416  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
417 #if ((PRU_SUART2_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
418  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
419 #else
420  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
421  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART2_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
422 #endif
423  pru_suart_regs->Reserved1 = 1;
424  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x100); /* SUART2 TX context base addr */
425  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)(MCASP_SRCTL_BASE_ADDR + (PRU_SUART2_CONFIG_TX_SER << 2));
426  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART2_CONFIG_TX_SER << 2));
427  pru_suart_tx_priv->buff_addr = 0x00E0; /* SUART2 TX formatted data base addr */
428 
429  /* Channel 3 is Rx context information */
430  pru_suart_regs++;
431  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
432  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART2_CONFIG_RX_SER);
433  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
434  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
435 #if ((PRU_SUART2_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
436  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
437 #else
438  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
439  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART2_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
440 #endif
441  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
442  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
443  pru_suart_regs->Reserved1 = 0;
444  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x110); /* SUART2 RX context base addr */
445  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART2_CONFIG_RX_SER << 2));
446  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART2_CONFIG_RX_SER << 2));
447 
448  /* ***************************** UART 2 **************************************** */
449  /* Channel 4 context information is Tx */
450  pru_suart_regs++;
451  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
452  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART3_CONFIG_TX_SER);
453  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
454  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
455 #if ((PRU_SUART3_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
456  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
457 #else
458  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
459  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART3_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
460 #endif
461  pru_suart_regs->Reserved1 = 1;
462  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x150); /* SUART3 TX context base addr */
463  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)( MCASP_SRCTL_BASE_ADDR + (PRU_SUART3_CONFIG_TX_SER << 2));
464  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART3_CONFIG_TX_SER << 2));
465  pru_suart_tx_priv->buff_addr = 0x0130; /* SUART3 TX formatted data base addr */
466 
467  /* Channel 5 is Rx context information */
468  pru_suart_regs++;
469  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
470  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART3_CONFIG_RX_SER);
471  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
472  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
473 #if ((PRU_SUART3_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
474  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
475 #else
476  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
477  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART3_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
478 #endif
479  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
480  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
481  pru_suart_regs->Reserved1 = 0;
482  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x160); /* SUART3 RX context base addr */
483  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART3_CONFIG_RX_SER << 2));
484  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART3_CONFIG_RX_SER << 2));
485 
486  /* ***************************** UART 3 **************************************** */
487  /* Channel 6 context information is Tx */
488  pru_suart_regs++;
489  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_TX;
490  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART4_CONFIG_TX_SER);
491  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
492  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
493 #if ((PRU_SUART4_CONFIG_DUPLEX & PRU_SUART_HALF_TX_DISABLED) == PRU_SUART_HALF_TX_DISABLED)
494  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
495 #else
496  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
497  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART4_CONFIG_TX_SER)) = MCASP_SRCTL_TX_MODE;
498 #endif
499  pru_suart_regs->Reserved1 = 1;
500  pru_suart_tx_priv = (pru_suart_tx_cntx_priv *) (pu32_pru_ram_base + 0x1A0); /* SUART4 TX context base addr */
501  pru_suart_tx_priv->asp_xsrctl_base = (unsigned int)(MCASP_SRCTL_BASE_ADDR + (PRU_SUART4_CONFIG_TX_SER << 2));
502  pru_suart_tx_priv->asp_xbuf_base = (unsigned int)(MCASP_XBUF_BASE_ADDR + (PRU_SUART4_CONFIG_TX_SER << 2));
503  pru_suart_tx_priv->buff_addr = 0x0180; /* SUART4 TX formatted data base addr */
504 
505  /* Channel 7 is Rx context information */
506  pru_suart_regs++;
507  pru_suart_regs->CH_Ctrl_Config1.mode = SUART_CHN_RX;
508  pru_suart_regs->CH_Ctrl_Config1.serializer_num = (0xF & PRU_SUART4_CONFIG_RX_SER);
509  pru_suart_regs->CH_Ctrl_Config1.over_sampling = SUART_DEFAULT_OVRSMPL;
510  pru_suart_regs->CH_Config2_TXRXStatus.bits_per_char = 8;
511 #if ((PRU_SUART4_CONFIG_DUPLEX & PRU_SUART_HALF_RX_DISABLED) == PRU_SUART_HALF_RX_DISABLED)
512  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_DISABLED;
513 #else
514  pru_suart_regs->CH_Config2_TXRXStatus.chn_state = SUART_CHN_ENABLED;
515  *((unsigned int *) (pu32SrCtlAddr + PRU_SUART4_CONFIG_RX_SER)) = MCASP_SRCTL_RX_MODE;
516 #endif
517  /* RX is active by default, write the dummy received data at PRU RAM addr 0x1FC to avoid memory corruption */
518  pru_suart_regs->CH_TXRXData = RX_DEFAULT_DATA_DUMP_ADDR;
519  pru_suart_regs->Reserved1 = 0;
520  pru_suart_rx_priv = (pru_suart_rx_cntx_priv *) (pu32_pru_ram_base + 0x1B0); /* SUART4 RX context base addr */
521  pru_suart_rx_priv->asp_rbuf_base = (unsigned int)(MCASP_RBUF_BASE_ADDR + (PRU_SUART4_CONFIG_RX_SER << 2));
522  pru_suart_rx_priv->asp_rsrctl_base = (unsigned int) (MCASP_SRCTL_BASE_ADDR + (PRU_SUART4_CONFIG_RX_SER << 2));
523 }
524 
525 #endif
526 
527 /*
528  * suart Initialization routine
529  */
530 short pru_softuart_init(unsigned int txBaudValue,
531  unsigned int rxBaudValue,
532  unsigned int oversampling,
533  unsigned char *pru_suart_emu_code,
534  unsigned int fw_size, arm_pru_iomap * arm_iomap_pru)
535 {
536  unsigned int omapl_addr;
537  unsigned int u32loop;
538  short status = PRU_SUART_SUCCESS;
539  short idx;
540  short retval;
541 
542  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) && (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
543  {
544  return PRU_SUART_FAILURE;
545  }
546 
547  pru_arm_iomap.pru_io_addr = arm_iomap_pru->pru_io_addr;
548  pru_arm_iomap.mcasp_io_addr = arm_iomap_pru->mcasp_io_addr;
549  pru_arm_iomap.psc0_io_addr = arm_iomap_pru->psc0_io_addr;
550  pru_arm_iomap.psc1_io_addr = arm_iomap_pru->psc1_io_addr;
551  pru_arm_iomap.syscfg_io_addr = arm_iomap_pru->syscfg_io_addr;
552  pru_arm_iomap.pFifoBufferPhysBase = arm_iomap_pru->pFifoBufferPhysBase;
553  pru_arm_iomap.pFifoBufferVirtBase = arm_iomap_pru->pFifoBufferVirtBase;
554  pru_arm_iomap.pru_clk_freq = arm_iomap_pru->pru_clk_freq;
555 
556  omapl_addr = (unsigned int)arm_iomap_pru->syscfg_io_addr;
557 
558  omapl_addr = (unsigned int)arm_iomap_pru->psc1_io_addr;
559  suart_mcasp_psc_enable(omapl_addr);
560 
561  omapl_addr = (unsigned int)arm_iomap_pru->mcasp_io_addr;
562  /* Configure McASP0 */
563  suart_mcasp_config(omapl_addr, txBaudValue, rxBaudValue, oversampling,
564  arm_iomap_pru);
565 
566  pru_enable(0, arm_iomap_pru);
567 #if (!(PRU1_MODE == PRU_MODE_INVALID))
568  pru_enable(1, arm_iomap_pru);
569 #endif
570 
571  omapl_addr = (unsigned int) arm_iomap_pru->pru_io_addr;
572 
573  for (u32loop = 0; u32loop < 512; u32loop++)
574  {
575  *(unsigned int *)(omapl_addr | u32loop) = 0x0;
576 #if (!(PRU1_MODE == PRU_MODE_INVALID))
577  *(unsigned int *)(omapl_addr | u32loop | 0x2000) = 0x0;
578 #endif
579  }
580 
581  pru_load(PRU_NUM0, (unsigned int *)pru_suart_emu_code,
582  (fw_size / sizeof(unsigned int)), arm_iomap_pru);
583 #if (!(PRU1_MODE == PRU_MODE_INVALID))
584  pru_load(PRU_NUM1, (unsigned int *)pru_suart_emu_code,
585  (fw_size / sizeof(unsigned int)), arm_iomap_pru);
586 #endif
587 
588  retval = arm_to_pru_intr_init();
589  if (-1 == retval) {
590  return status;
591  }
592  pru_set_delay_count (pru_arm_iomap.pru_clk_freq);
593 
594  suart_set_pru_id(0);
595 
596 #if (!(PRU1_MODE == PRU_MODE_INVALID))
597  suart_set_pru_id(1);
598 #endif
599 
600  pru_set_rx_tx_mode(PRU0_MODE, PRU_NUM0);
601 #if (!(PRU1_MODE == PRU_MODE_INVALID))
602  pru_set_rx_tx_mode(PRU1_MODE, PRU_NUM1);
603 #endif
604 
605  pru_set_ram_data (arm_iomap_pru);
606 
607  pru_run(PRU_NUM0, arm_iomap_pru);
608 #if (!(PRU1_MODE == PRU_MODE_INVALID))
609  pru_run(PRU_NUM1, arm_iomap_pru);
610 #endif
611 
612  /* Initialize gUartStatuTable */
613  for (idx = 0; idx < 8; idx++) {
614  gUartStatuTable[idx] = ePRU_SUART_UART_FREE;
615  }
616 
617  return status;
618 }
619 
620 static void pru_set_rx_tx_mode(Uint32 pru_mode, Uint32 pruNum)
621 {
622 
623  unsigned int pruOffset;
624 
625  if (pruNum == PRU_NUM0)
626  {
627  /* PRU0 */
628  pruOffset = PRU_SUART_PRU0_RX_TX_MODE;
629  }
630  else if (pruNum == PRU_NUM1) {
631  /* PRU1 */
632  pruOffset = PRU_SUART_PRU1_RX_TX_MODE;
633  }
634  else
635  {
636  return;
637  }
638 
639  pru_ram_write_data(pruOffset, (Uint8 *)&pru_mode, 1, &pru_arm_iomap);
640 
641 }
642 
643 
644 void pru_set_fifo_timeout(Uint32 timeout)
645 {
646  /* PRU 0 */
647  pru_ram_write_data(PRU_SUART_PRU0_IDLE_TIMEOUT_OFFSET,
648  (Uint8 *)&timeout, 2, &pru_arm_iomap);
649 #if (!(PRU1_MODE == PRU_MODE_INVALID))
650  /* PRU 1 */
651  pru_ram_write_data(PRU_SUART_PRU1_IDLE_TIMEOUT_OFFSET,
652  (Uint8 *)&timeout, 2, &pru_arm_iomap);
653 #endif
654 }
655 
656 /* Not needed as PRU Soft Uart Firmware is implemented as Mcasp Event Based */
657 static void pru_set_delay_count (Uint32 pru_freq)
658 {
659  Uint32 u32delay_cnt;
660 
661  if (pru_freq == 228 )
662  {
663  u32delay_cnt = 5;
664  }else if (pru_freq == 186)
665  {
666  u32delay_cnt = 5;
667  }
668  else
669  {
670  u32delay_cnt =3;
671  }
672 
673  /* PRU 0 */
674  pru_ram_write_data(PRU_SUART_PRU0_DELAY_OFFSET,
675  (Uint8 *)&u32delay_cnt, 1, &pru_arm_iomap);
676 #if (!(PRU1_MODE == PRU_MODE_INVALID))
677  /* PRU 1 */
678  pru_ram_write_data(PRU_SUART_PRU1_DELAY_OFFSET,
679  (Uint8 *)&u32delay_cnt, 1, &pru_arm_iomap);
680 #endif
681 
682 }
683 
684 void pru_mcasp_deinit (void)
685 {
686  suart_mcasp_reset (&pru_arm_iomap);
687 }
688 
689 short pru_softuart_deinit(void)
690 {
691  unsigned int offset;
692  short s16retval = 0;
693  unsigned int u32value = 0;
694 
695  pru_disable(&pru_arm_iomap);
696 
697  offset =
698  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT1 &
699  0xFFFF);
700  u32value = 0xFFFFFFFF;
701  s16retval =
702  pru_ram_write_data_4byte(offset, (unsigned int *)&u32value, 1);
703  if (-1 == s16retval) {
704  return -1;
705  }
706  offset =
707  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT0 &
708  0xFFFF);
709  u32value = 0xFFFFFFFF;
710  s16retval =
711  pru_ram_write_data_4byte(offset, (unsigned int *)&u32value, 1);
712  if (-1 == s16retval) {
713  return -1;
714  }
715 
716  return PRU_SUART_SUCCESS;
717 }
718 
719 /*
720  * suart Instance open routine
721  */
722 short pru_softuart_open(suart_handle hSuart)
723 {
724  short status = PRU_SUART_SUCCESS;
725 
726  switch (hSuart->uartNum) {
727  /* ************ PRU 0 ************** */
728  case PRU_SUART_UART1:
729  if (gUartStatuTable[PRU_SUART_UART1 - 1] ==
730  ePRU_SUART_UART_IN_USE) {
731  status = SUART_UART_IN_USE;
732  return status;
733  } else {
734  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
735  hSuart->uartType = PRU_SUART1_CONFIG_DUPLEX;
736  hSuart->uartTxChannel = PRU_SUART1_CONFIG_TX_SER;
737  hSuart->uartRxChannel = PRU_SUART1_CONFIG_RX_SER;
738 
739  gUartStatuTable[PRU_SUART_UART1 - 1] =
740  ePRU_SUART_UART_IN_USE;
741  }
742 
743  break;
744 
745  case PRU_SUART_UART2:
746  if (gUartStatuTable[PRU_SUART_UART2 - 1] ==
747  ePRU_SUART_UART_IN_USE) {
748  status = SUART_UART_IN_USE;
749  return status;
750  } else {
751 
752  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
753  hSuart->uartType = PRU_SUART2_CONFIG_DUPLEX;
754  hSuart->uartTxChannel = PRU_SUART2_CONFIG_TX_SER;
755  hSuart->uartRxChannel = PRU_SUART2_CONFIG_RX_SER;
756 
757  gUartStatuTable[PRU_SUART_UART2 - 1] =
758  ePRU_SUART_UART_IN_USE;
759  }
760 
761  break;
762 
763  case PRU_SUART_UART3:
764  if (gUartStatuTable[PRU_SUART_UART3 - 1] ==
765  ePRU_SUART_UART_IN_USE) {
766  status = SUART_UART_IN_USE;
767  return status;
768  } else {
769 
770  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
771  hSuart->uartType = PRU_SUART3_CONFIG_DUPLEX;
772  hSuart->uartTxChannel = PRU_SUART3_CONFIG_TX_SER;
773  hSuart->uartRxChannel = PRU_SUART3_CONFIG_RX_SER;
774 
775  gUartStatuTable[PRU_SUART_UART3 - 1] =
776  ePRU_SUART_UART_IN_USE;
777  }
778 
779  break;
780 
781  case PRU_SUART_UART4:
782  if (gUartStatuTable[PRU_SUART_UART4 - 1] ==
783  ePRU_SUART_UART_IN_USE) {
784  status = SUART_UART_IN_USE;
785  return status;
786  } else {
787 
788  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
789  hSuart->uartType = PRU_SUART4_CONFIG_DUPLEX;
790  hSuart->uartTxChannel = PRU_SUART4_CONFIG_TX_SER;
791  hSuart->uartRxChannel = PRU_SUART4_CONFIG_RX_SER;
792 
793  gUartStatuTable[PRU_SUART_UART4 - 1] =
794  ePRU_SUART_UART_IN_USE;
795  }
796  break;
797 
798  /* ************ PRU 1 ************** */
799  case PRU_SUART_UART5:
800  if (gUartStatuTable[PRU_SUART_UART5 - 1] ==
801  ePRU_SUART_UART_IN_USE) {
802  status = SUART_UART_IN_USE;
803  return status;
804  } else {
805  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
806  hSuart->uartType = PRU_SUART5_CONFIG_DUPLEX;
807  hSuart->uartTxChannel = PRU_SUART5_CONFIG_TX_SER;
808  hSuart->uartRxChannel = PRU_SUART5_CONFIG_RX_SER;
809 
810  gUartStatuTable[PRU_SUART_UART5 - 1] =
811  ePRU_SUART_UART_IN_USE;
812  }
813  break;
814 
815  case PRU_SUART_UART6:
816  if (gUartStatuTable[PRU_SUART_UART6 - 1] ==
817  ePRU_SUART_UART_IN_USE) {
818  status = SUART_UART_IN_USE;
819  return status;
820  } else {
821  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
822  hSuart->uartType = PRU_SUART6_CONFIG_DUPLEX;
823  hSuart->uartTxChannel = PRU_SUART6_CONFIG_TX_SER;
824  hSuart->uartRxChannel = PRU_SUART6_CONFIG_RX_SER;
825 
826  gUartStatuTable[PRU_SUART_UART6 - 1] =
827  ePRU_SUART_UART_IN_USE;
828  }
829 
830  break;
831 
832  case PRU_SUART_UART7:
833  if (gUartStatuTable[PRU_SUART_UART7 - 1] ==
834  ePRU_SUART_UART_IN_USE) {
835  status = SUART_UART_IN_USE;
836  return status;
837  } else {
838  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
839  hSuart->uartType = PRU_SUART7_CONFIG_DUPLEX;
840  hSuart->uartTxChannel = PRU_SUART7_CONFIG_TX_SER;
841  hSuart->uartRxChannel = PRU_SUART7_CONFIG_RX_SER;
842 
843  gUartStatuTable[PRU_SUART_UART7 - 1] =
844  ePRU_SUART_UART_IN_USE;
845  }
846  break;
847 
848  case PRU_SUART_UART8:
849  if (gUartStatuTable[PRU_SUART_UART8 - 1] ==
850  ePRU_SUART_UART_IN_USE) {
851  status = SUART_UART_IN_USE;
852  return status;
853  } else {
854  hSuart->uartStatus = ePRU_SUART_UART_IN_USE;
855  hSuart->uartType = PRU_SUART8_CONFIG_DUPLEX;
856  hSuart->uartTxChannel = PRU_SUART8_CONFIG_TX_SER;
857  hSuart->uartRxChannel = PRU_SUART8_CONFIG_RX_SER;
858 
859  gUartStatuTable[PRU_SUART_UART8 - 1] =
860  ePRU_SUART_UART_IN_USE;
861  }
862  break;
863 
864  default:
865  /* return invalid UART */
866  status = SUART_INVALID_UART_NUM;
867  break;
868  }
869  return (status);
870 }
871 
872 /*
873  * suart instance close routine
874  */
875 short pru_softuart_close(suart_handle hUart)
876 {
877  short status = SUART_SUCCESS;
878 
879  if (hUart == NULL) {
880  return (PRU_SUART_ERR_HANDLE_INVALID);
881  } else {
882  gUartStatuTable[hUart->uartNum - 1] = ePRU_SUART_UART_FREE;
883  /* Reset the Instance to Invalid */
884  hUart->uartNum = PRU_SUART_UARTx_INVALID;
885  hUart->uartStatus = ePRU_SUART_UART_FREE;
886  }
887  return (status);
888 }
889 
890 /*
891  * suart routine for setting relative baud rate
892  */
893 short pru_softuart_setbaud
894  (suart_handle hUart,
895  unsigned short txClkDivisor,
896  unsigned short rxClkDivisor)
897 {
898  unsigned int offset;
899  unsigned int pruOffset;
900  short status = SUART_SUCCESS;
901  unsigned short chNum;
902  unsigned short regval = 0;
903 
904  if (hUart == NULL)
905  {
906  return (PRU_SUART_ERR_HANDLE_INVALID);
907  }
908 
909  /* Set the clock divisor value into the McASP */
910  if ((txClkDivisor > 385) || (txClkDivisor == 0))
911  {
912  return SUART_INVALID_CLKDIVISOR;
913  }
914 
915  if ((rxClkDivisor > 385) || (rxClkDivisor == 0))
916  {
917  return SUART_INVALID_CLKDIVISOR;
918  }
919 
920 
921  chNum = hUart->uartNum - 1;
922 
923  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
924  {
925  /* channel starts from 0 and uart instance starts from 1 */
926  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
927 
928  if (hUart->uartNum <= 4)
929  {
930  /* PRU0 */
931  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
932  } else {
933  /* PRU1 */
934  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
935  /* First 8 channel corresponds to PRU0 */
936  chNum -= 8;
937  }
938  }
939  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
940  {
941  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
942  }
943  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
944  {
945  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
946  }
947  else
948  {
949  return PRU_MODE_INVALID;
950  }
951 
952 
953 
954 
955  if (txClkDivisor != 0)
956  {
957  offset =
958  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
959  PRU_SUART_CH_CONFIG1_OFFSET;
960  pru_ram_read_data(offset, (Uint8 *) &regval, 2,
961  &pru_arm_iomap);
962  regval &= (~0x3FF);
963  regval |= txClkDivisor;
964  pru_ram_write_data(offset, (Uint8 *) &regval, 2,
965  &pru_arm_iomap);
966  }
967 
968  if (PRU0_MODE == PRU_MODE_RX_ONLY )
969  {
970  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
971  }
972  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
973  {
974  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
975  }
976  else if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
977  {
978  chNum++;
979  }
980  else
981  {
982  return PRU_MODE_INVALID;
983  }
984 
985  regval = 0;
986  if (rxClkDivisor != 0)
987  {
988  offset =
989  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
990  PRU_SUART_CH_CONFIG1_OFFSET;
991  pru_ram_read_data(offset, (Uint8 *) &regval, 2,
992  &pru_arm_iomap);
993  regval &= (~0x3FF);
994  regval |= txClkDivisor;
995  pru_ram_write_data(offset, (Uint8 *) &regval, 2,
996  &pru_arm_iomap);
997  }
998  return status;
999 }
1000 
1001 /*
1002  * suart routine for setting number of bits per character for a specific uart
1003  */
1004 short pru_softuart_setdatabits
1005  (suart_handle hUart, unsigned short txDataBits, unsigned short rxDataBits) {
1006  unsigned int offset;
1007  unsigned int pruOffset;
1008  short status = SUART_SUCCESS;
1009  unsigned short chNum;
1010  unsigned int reg_val;
1011 
1012  if (hUart == NULL) {
1013  return (PRU_SUART_ERR_HANDLE_INVALID);
1014  }
1015 
1016  /*
1017  * NOTE:
1018  * The supported data bits are 6, 7, 8, 9, 10, 11 and 12 bits per character
1019  */
1020 
1021  if ((txDataBits < ePRU_SUART_DATA_BITS6) || (txDataBits > ePRU_SUART_DATA_BITS12)) {
1022  return PRU_SUART_ERR_PARAMETER_INVALID;
1023  }
1024 
1025  if ((rxDataBits < ePRU_SUART_DATA_BITS6) || (rxDataBits > ePRU_SUART_DATA_BITS12)) {
1026  return PRU_SUART_ERR_PARAMETER_INVALID;
1027  }
1028 
1029  chNum = hUart->uartNum - 1;
1030 
1031  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1032  {
1033  /* channel starts from 0 and uart instance starts from 1 */
1034  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1035 
1036  if (hUart->uartNum <= 4)
1037  {
1038  /* PRU0 */
1039  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1040  } else {
1041  /* PRU1 */
1042  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1043  /* First 8 channel corresponds to PRU0 */
1044  chNum -= 8;
1045  }
1046  }
1047  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1048  {
1049  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1050  }
1051  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1052  {
1053  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1054  }
1055  else
1056  {
1057  return PRU_MODE_INVALID;
1058  }
1059 
1060 
1061  if (txDataBits != 0) {
1062  offset =
1063  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1064  PRU_SUART_CH_CONFIG2_OFFSET;
1065  pru_ram_read_data(offset, (Uint8 *) &reg_val, 1,
1066  &pru_arm_iomap);
1067 
1068  reg_val &= ~(0xF);
1069  reg_val |= txDataBits;
1070  pru_ram_write_data(offset, (Uint8 *) &reg_val, 1,
1071  &pru_arm_iomap);
1072  }
1073 
1074  if (PRU0_MODE == PRU_MODE_RX_ONLY )
1075  {
1076  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1077  }
1078  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1079  {
1080  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1081  }
1082  else if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1083  {
1084  chNum++;
1085  }
1086  else
1087  {
1088  return PRU_MODE_INVALID;
1089  }
1090 
1091  if (rxDataBits != 0) {
1092  offset =
1093  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1094  PRU_SUART_CH_CONFIG2_OFFSET;
1095 
1096  pru_ram_read_data(offset, (Uint8 *) &reg_val, 1,
1097  &pru_arm_iomap);
1098 
1099  reg_val &= ~(0xF);
1100  reg_val |= rxDataBits;
1101 
1102  pru_ram_write_data(offset, (Uint8 *) & rxDataBits, 1,
1103  &pru_arm_iomap);
1104  }
1105 
1106  return (status);
1107 }
1108 
1109 /*
1110  * suart routine to configure specific uart
1111  */
1112 short pru_softuart_setconfig(suart_handle hUart, suart_config * configUart)
1113 {
1114  unsigned int offset;
1115  unsigned int pruOffset;
1116  short status = SUART_SUCCESS;
1117  unsigned short chNum;
1118  unsigned short regVal = 0;
1119  if (hUart == NULL) {
1120  return (PRU_SUART_ERR_HANDLE_INVALID);
1121  }
1122 
1123  /*
1124  * NOTE:
1125  * Dependent baud rate for the given UART, the value MUST BE LESS THAN OR
1126  * EQUAL TO 64, preScalarValue <= 64
1127  */
1128  /* Validate the value of relative buad rate */
1129  if ((configUart->txClkDivisor > 384) || (configUart->rxClkDivisor > 384)) {
1130  return SUART_INVALID_CLKDIVISOR;
1131  }
1132  /* Validate the bits per character */
1133  if ((configUart->txBitsPerChar < 8) || (configUart->txBitsPerChar > 14)) {
1134  return PRU_SUART_ERR_PARAMETER_INVALID;
1135  }
1136 
1137  if ((configUart->rxBitsPerChar < 8) || (configUart->rxBitsPerChar > 14)) {
1138  return PRU_SUART_ERR_PARAMETER_INVALID;
1139  }
1140 
1141  chNum = hUart->uartNum - 1;
1142 
1143  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1144  {
1145 
1146  /* channel starts from 0 and uart instance starts from 1 */
1147  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1148 
1149  if (hUart->uartNum <= 4)
1150  {
1151  /* PRU0 */
1152  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1153  } else {
1154  /* PRU1 */
1155  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1156  /* First 8 channel corresponds to PRU0 */
1157  chNum -= 8;
1158  }
1159  }
1160  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1161  {
1162  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1163  }
1164  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1165  {
1166  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1167  }
1168  else
1169  {
1170  return PRU_MODE_INVALID;
1171  }
1172 
1173  /* Configuring the Transmit part of the given UART */
1174  if (configUart->TXSerializer != PRU_SUART_SERIALIZER_NONE) {
1175  /* Serializer has been as TX in mcasp config, by writing 1 in bits corresponding to tx serializer
1176  in PFUNC regsiter i.e. already set to GPIO mode PRU code will set then back to MCASP mode once
1177  TX request for that serializer is posted. It is required because at this point Mcasp is accessed
1178  by both PRU and DSP have lower priority for Mcasp in comparison to PRU and DPS keeps on looping
1179  there only.
1180  */
1181 
1182  /*
1183  suart_mcasp_tx_serialzier_set (configUart->TXSerializer, &pru_arm_iomap);
1184  */
1185 
1186  /* Configuring TX serializer */
1187  offset =
1188  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1189  PRU_SUART_CH_CTRL_OFFSET;
1190  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1191  &pru_arm_iomap);
1192 
1193  regVal = (configUart->TXSerializer <<
1194  PRU_SUART_CH_CTRL_SR_SHIFT);
1195 
1196  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1197  &pru_arm_iomap);
1198  /* Configuring the Transmit part of the given UART */
1199  /* Configuring TX prescalar value */
1200  offset =
1201  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1202  PRU_SUART_CH_CONFIG1_OFFSET;
1203  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1204  &pru_arm_iomap);
1205  regVal =
1206  regVal | (configUart->txClkDivisor <<
1207  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1208  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1209  &pru_arm_iomap);
1210  /* Configuring TX bits per character value */
1211  offset =
1212  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1213  PRU_SUART_CH_CONFIG2_OFFSET;
1214  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1215  &pru_arm_iomap);
1216  regVal =
1217  regVal | (configUart->txBitsPerChar <<
1218  PRU_SUART_CH_CONFIG2_BITPERCHAR_SHIFT);
1219  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1220  &pru_arm_iomap);
1221  }
1222 
1223  if (PRU0_MODE == PRU_MODE_RX_ONLY )
1224  {
1225  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1226  }
1227  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1228  {
1229  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1230  }
1231  else if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1232  {
1233  chNum++;
1234  }
1235  else
1236  {
1237  return PRU_MODE_INVALID;
1238  }
1239 
1240  /* Configuring the Transmit part of the given UART */
1241  if (configUart->RXSerializer != PRU_SUART_SERIALIZER_NONE) {
1242  /* Configuring RX serializer */
1243  offset =
1244  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1245  PRU_SUART_CH_CTRL_OFFSET;
1246  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1247  &pru_arm_iomap);
1248 
1249  regVal = (configUart->RXSerializer <<
1250  PRU_SUART_CH_CTRL_SR_SHIFT);
1251  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1252  &pru_arm_iomap);
1253 
1254  /* Configuring RX prescalar value and Oversampling */
1255  offset =
1256  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1257  PRU_SUART_CH_CONFIG1_OFFSET;
1258  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1259  &pru_arm_iomap);
1260  regVal =
1261  regVal | (configUart->rxClkDivisor <<
1262  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT) |
1263  (configUart->Oversampling <<
1264  PRU_SUART_CH_CONFIG1_OVS_SHIFT);
1265  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1266  &pru_arm_iomap);
1267 
1268  /* Configuring RX bits per character value */
1269  offset =
1270  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1271  PRU_SUART_CH_CONFIG2_OFFSET;
1272  pru_ram_read_data(offset, (Uint8 *) & regVal, 2,
1273  &pru_arm_iomap);
1274  regVal =
1275  regVal | (configUart->rxBitsPerChar <<
1276  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1277  pru_ram_write_data(offset, (Uint8 *) & regVal, 2,
1278  &pru_arm_iomap);
1279  }
1280  return (status);
1281 }
1282 
1283 /*
1284  * suart routine for getting the number of bytes transfered
1285  */
1286 short pru_softuart_getTxDataLen(suart_handle hUart)
1287 {
1288  unsigned int offset;
1289  unsigned int pruOffset;
1290  unsigned short chNum;
1291  unsigned short u16ReadValue = 0;
1292 
1293  if (hUart == NULL) {
1294  return (PRU_SUART_ERR_HANDLE_INVALID);
1295  }
1296 
1297  chNum = hUart->uartNum - 1;
1298 
1299  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1300  {
1301  /* channel starts from 0 and uart instance starts from 1 */
1302  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1303 
1304  if (hUart->uartNum <= 4)
1305  {
1306  /* PRU0 */
1307  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1308  } else {
1309  /* PRU1 */
1310  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1311  /* First 8 channel corresponds to PRU0 */
1312  chNum -= 8;
1313  }
1314  }
1315  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1316  {
1317  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1318  }
1319  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1320  {
1321  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1322  }
1323  else
1324  {
1325  return PRU_MODE_INVALID;
1326  }
1327 
1328  /* Transmit channel number is (UartNum * 2) - 2 */
1329 
1330  offset =
1331  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1332  PRU_SUART_CH_CONFIG2_OFFSET;
1333  pru_ram_read_data(offset, (Uint8 *) & u16ReadValue, 2, &pru_arm_iomap);
1334 
1335  u16ReadValue = ((u16ReadValue & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1336  PRU_SUART_CH_CONFIG2_DATALEN_SHIFT);
1337  return (u16ReadValue);
1338 }
1339 
1340 /*
1341  * suart routine for getting the number of bytes received
1342  */
1343 short pru_softuart_getRxDataLen(suart_handle hUart)
1344 {
1345  unsigned int offset;
1346  unsigned int pruOffset;
1347  unsigned short chNum;
1348  unsigned short u16ReadValue = 0;
1349 
1350  if (hUart == NULL) {
1351  return (PRU_SUART_ERR_HANDLE_INVALID);
1352  }
1353 
1354  chNum = hUart->uartNum - 1;
1355 
1356  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1357  {
1358  /* channel starts from 0 and uart instance starts from 1 */
1359  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1360 
1361  if (hUart->uartNum <= 4)
1362  {
1363  /* PRU0 */
1364  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1365  } else {
1366  /* PRU1 */
1367  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1368  /* First 8 channel corresponds to PRU0 */
1369  chNum -= 8;
1370  }
1371 
1372  chNum++;
1373  }
1374  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
1375  {
1376  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1377  }
1378  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1379  {
1380  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1381  }
1382  else
1383  {
1384  return PRU_MODE_INVALID;
1385  }
1386 
1387  offset =
1388  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1389  PRU_SUART_CH_CONFIG2_OFFSET;
1390  pru_ram_read_data(offset, (Uint8 *) & u16ReadValue, 2, &pru_arm_iomap);
1391 
1392  u16ReadValue = ((u16ReadValue & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1393  PRU_SUART_CH_CONFIG2_DATALEN_SHIFT);
1394 
1395  return (u16ReadValue);
1396 }
1397 
1398 /*
1399  * suart routine to get the configuration information from a specific uart
1400  */
1401 short pru_softuart_getconfig(suart_handle hUart, suart_config * configUart)
1402 {
1403  unsigned int offset;
1404  unsigned int pruOffset;
1405  unsigned short chNum;
1406  unsigned short regVal = 0;
1407  short status = SUART_SUCCESS;
1408 
1409  if (hUart == NULL) {
1410  return (PRU_SUART_ERR_HANDLE_INVALID);
1411  }
1412 
1413  /*
1414  * NOTE:
1415  * Dependent baud rate for the given UART, the value MUST BE LESS THAN OR
1416  * EQUAL TO 64, preScalarValue <= 64
1417  */
1418 
1419  chNum = hUart->uartNum - 1;
1420  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1421  {
1422  /* channel starts from 0 and uart instance starts from 1 */
1423  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1424 
1425 
1426  if (hUart->uartNum <= 4)
1427  {
1428  /* PRU0 */
1429  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1430  } else {
1431  /* PRU1 */
1432  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1433  /* First 8 channel corresponds to PRU0 */
1434  chNum -= 8;
1435  }
1436  }
1437  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1438  {
1439  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1440  }
1441  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1442  {
1443  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1444  }
1445  else
1446  {
1447  return PRU_MODE_INVALID;
1448  }
1449 
1450  /* Configuring the Transmit part of the given UART */
1451  /* Configuring TX serializer */
1452  offset =
1453  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1454  PRU_SUART_CH_CTRL_OFFSET;
1455  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1456  configUart->TXSerializer =
1457  ((regVal & PRU_SUART_CH_CTRL_SR_MASK) >>
1458  PRU_SUART_CH_CTRL_SR_SHIFT);
1459 
1460  /* Configuring TX prescalar value */
1461  offset =
1462  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1463  PRU_SUART_CH_CONFIG1_OFFSET;
1464  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1465  configUart->txClkDivisor =
1466  ((regVal & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1467  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1468 
1469  /* Configuring TX bits per character value */
1470  offset =
1471  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1472  PRU_SUART_CH_CONFIG2_OFFSET;
1473  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1474  configUart->txBitsPerChar =
1475  ((regVal & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1476  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1477 
1478  if (PRU0_MODE == PRU_MODE_RX_ONLY )
1479  {
1480  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1481  }
1482  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1483  {
1484  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1485  }
1486  else if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1487  {
1488  chNum++;
1489  }
1490  else
1491  {
1492  return PRU_MODE_INVALID;
1493  }
1494 
1495  /* Configuring the Transmit part of the given UART */
1496  /* Configuring RX serializer */
1497  offset =
1498  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1499  PRU_SUART_CH_CTRL_OFFSET;
1500  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1501  configUart->RXSerializer =
1502  ((regVal & PRU_SUART_CH_CTRL_SR_MASK) >>
1503  PRU_SUART_CH_CTRL_SR_SHIFT);
1504 
1505  /* Configuring RX prescalar value and Oversampling */
1506  offset =
1507  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1508  PRU_SUART_CH_CONFIG1_OFFSET;
1509  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1510  configUart->rxClkDivisor =
1511  ((regVal & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1512  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1513  configUart->Oversampling =
1514  ((regVal & PRU_SUART_CH_CONFIG1_OVS_MASK) >>
1515  PRU_SUART_CH_CONFIG1_OVS_SHIFT);
1516 
1517  /* Configuring RX bits per character value */
1518  offset =
1519  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1520  PRU_SUART_CH_CONFIG2_OFFSET;
1521  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1522  configUart->rxBitsPerChar =
1523  ((regVal & PRU_SUART_CH_CONFIG1_DIVISOR_MASK) >>
1524  PRU_SUART_CH_CONFIG1_DIVISOR_SHIFT);
1525 
1526  return (status);
1527 }
1528 
1529 
1530 int pru_softuart_pending_tx_request(void)
1531 {
1532  unsigned int offset = 0;
1533  unsigned int u32ISRValue = 0;
1534 
1535  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1536  {
1537  return SUART_SUCCESS;
1538  }
1539  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1540  {
1541  /* Read PRU Interrupt Status Register from PRU */
1542  offset =
1543  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT1 &
1544  0xFFFF);
1545  pru_ram_read_data_4byte(offset, (unsigned int *)&u32ISRValue, 1);
1546 
1547  if ((u32ISRValue & 0x1) == 0x1)
1548  {
1549  return PRU_SUART_FAILURE;
1550  }
1551  }
1552  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1553  {
1554  /* Read PRU Interrupt Status Register from PRU */
1555  offset =
1556  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT1 &
1557  0xFFFF);
1558  pru_ram_read_data_4byte(offset, (unsigned int *)&u32ISRValue, 1);
1559 
1560  if ((u32ISRValue & 0x2) == 0x2)
1561  {
1562  return PRU_SUART_FAILURE;
1563  }
1564  }
1565  else
1566  {
1567  return PRU_MODE_INVALID;
1568  }
1569 
1570  return SUART_SUCCESS;
1571 }
1572 
1573 /*
1574  * suart data transmit routine
1575  */
1576 short pru_softuart_write
1577  (suart_handle hUart, unsigned int *ptTxDataBuf, unsigned short dataLen) {
1578  unsigned int offset = 0;
1579  unsigned int pruOffset;
1580  short status = SUART_SUCCESS;
1581  unsigned short chNum;
1582  unsigned short regVal = 0;
1583 
1584  unsigned short pru_num;
1585 
1586  if (hUart == NULL) {
1587  return (PRU_SUART_ERR_HANDLE_INVALID);
1588  }
1589 
1590  chNum = hUart->uartNum - 1;
1591 
1592  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1593  {
1594 
1595  /* channel starts from 0 and uart instance starts from 1 */
1596  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1597 
1598  if (hUart->uartNum <= 4)
1599  {
1600  /* PRU0 */
1601  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1602  pru_num = hUart->uartNum;
1603  } else {
1604  /* PRU1 */
1605  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1606  /* First 8 channel corresponds to PRU0 */
1607  chNum -= 8;
1608  pru_num = hUart->uartNum;
1609  }
1610  }
1611  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1612  {
1613  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1614  pru_num = 0;
1615  }
1616  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
1617  {
1618  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1619  pru_num = 1;
1620  }
1621  else
1622  {
1623  return PRU_MODE_INVALID;
1624  }
1625 
1626  /* Writing data length to SUART channel register */
1627  offset =
1628  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1629  PRU_SUART_CH_CONFIG2_OFFSET;
1630  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1631  regVal &= ~PRU_SUART_CH_CONFIG2_DATALEN_MASK;
1632  regVal = regVal | (dataLen << PRU_SUART_CH_CONFIG2_DATALEN_SHIFT);
1633  pru_ram_write_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1634 
1635  /* Writing the data pointer to channel TX data pointer */
1636  offset =
1637  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1638  PRU_SUART_CH_TXRXDATA_OFFSET;
1639  pru_ram_write_data(offset, (Uint8 *) ptTxDataBuf, 4, &pru_arm_iomap);
1640 
1641  /* Service Request to PRU */
1642  offset =
1643  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1644  PRU_SUART_CH_CTRL_OFFSET;
1645  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1646 
1647  regVal &= ~(PRU_SUART_CH_CTRL_MODE_MASK |PRU_SUART_CH_CTRL_SREQ_MASK);
1648 
1649  regVal |= (PRU_SUART_CH_CTRL_TX_MODE << PRU_SUART_CH_CTRL_MODE_SHIFT) |
1650  (PRU_SUART_CH_CTRL_SREQ << PRU_SUART_CH_CTRL_SREQ_SHIFT);
1651 
1652  pru_ram_write_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1653 
1654  /* generate ARM->PRU event */
1655  suart_arm_to_pru_intr(pru_num);
1656 
1657  return (status);
1658 }
1659 
1660 /*
1661  * suart data receive routine
1662  */
1663 short pru_softuart_read
1664  (suart_handle hUart, unsigned int *ptDataBuf, unsigned short dataLen) {
1665  unsigned int offset = 0;
1666  unsigned int pruOffset;
1667  short status = SUART_SUCCESS;
1668  unsigned short chNum;
1669  unsigned short regVal = 0;
1670  unsigned short pru_num;
1671  if (hUart == NULL) {
1672  return (PRU_SUART_ERR_HANDLE_INVALID);
1673  }
1674 
1675  chNum = hUart->uartNum - 1;
1676 
1677  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1678  {
1679  /* channel starts from 0 and uart instance starts from 1 */
1680  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1681 
1682  if (hUart->uartNum <= 4)
1683  {
1684  /* PRU0 */
1685  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1686  pru_num = hUart->uartNum;
1687  } else {
1688  /* PRU1 */
1689  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1690  /* First 8 channel corresponds to PRU0 */
1691  chNum -= 8;
1692  pru_num = hUart->uartNum;
1693  }
1694  chNum++;
1695  }
1696  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
1697  {
1698  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1699  pru_num = 0;
1700  }
1701  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1702  {
1703  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1704  pru_num = 1;
1705  }
1706  else
1707  {
1708  return PRU_MODE_INVALID;
1709  }
1710 
1711  /* Writing data length to SUART channel register */
1712  offset =
1713  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1714  PRU_SUART_CH_CONFIG2_OFFSET;
1715  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1716  regVal &= ~PRU_SUART_CH_CONFIG2_DATALEN_MASK;
1717  regVal = regVal | (dataLen << PRU_SUART_CH_CONFIG2_DATALEN_SHIFT);
1718  pru_ram_write_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1719 
1720  /* Writing the data pointer to channel RX data pointer */
1721  offset =
1722  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1723  PRU_SUART_CH_TXRXDATA_OFFSET;
1724  pru_ram_write_data(offset, (Uint8 *) ptDataBuf, 4, &pru_arm_iomap);
1725 
1726  /* Service Request to PRU */
1727  offset =
1728  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1729  PRU_SUART_CH_CTRL_OFFSET;
1730 
1731 
1732  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1733 
1734  regVal &= ~(PRU_SUART_CH_CTRL_MODE_MASK |PRU_SUART_CH_CTRL_SREQ_MASK);
1735 
1736  regVal |= ( PRU_SUART_CH_CTRL_RX_MODE << PRU_SUART_CH_CTRL_MODE_SHIFT) |
1737  (PRU_SUART_CH_CTRL_SREQ << PRU_SUART_CH_CTRL_SREQ_SHIFT);
1738 
1739  pru_ram_write_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
1740 
1741  /* enable the timeout interrupt */
1742  suart_intr_setmask (hUart->uartNum, PRU_RX_INTR, CHN_TXRX_IE_MASK_TIMEOUT);
1743 
1744  /* generate ARM->PRU event */
1745  suart_arm_to_pru_intr(pru_num);
1746 
1747  return (status);
1748 }
1749 
1750 /*
1751  * suart routine to read the data from the RX FIFO
1752  */
1753 short pru_softuart_read_data (
1754  suart_handle hUart,
1755  Uint8 * pDataBuffer,
1756  Int32 s32MaxLen,
1757  Uint32 * pu32DataRead)
1758 {
1759  short retVal = PRU_SUART_SUCCESS;
1760  Uint8 * pu8SrcAddr = NULL;
1761  Uint32 u32DataRead = 0;
1762  Uint32 u32DataLen = 0;
1763  Uint32 u32CharLen = 0;
1764  unsigned int offset = 0;
1765  unsigned int pruOffset;
1766  unsigned short chNum;
1767  unsigned short u16Status = 0;
1768 
1769  if (hUart == NULL) {
1770  return (PRU_SUART_ERR_HANDLE_INVALID);
1771  }
1772 
1773  chNum = hUart->uartNum - 1;
1774  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1775  {
1776  /* channel starts from 0 and uart instance starts from 1 */
1777  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1778 
1779  if (hUart->uartNum <= 4)
1780  {
1781  /* PRU0 */
1782  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1783  } else {
1784  /* PRU1 */
1785  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1786  /* First 8 channel corresponds to PRU0 */
1787  chNum -= 8;
1788  }
1789  chNum++;
1790  }
1791  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
1792  {
1793  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1794  }
1795  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1796  {
1797  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1798  }
1799  else
1800  {
1801  return PRU_MODE_INVALID;
1802  }
1803 
1804  /* Get the data pointer from channel RX data pointer */
1805  offset =
1806  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1807  PRU_SUART_CH_TXRXDATA_OFFSET;
1808  pru_ram_read_data(offset, (Uint8 *) &pu8SrcAddr, 4, &pru_arm_iomap);
1809 
1810  /* Reading data length from SUART channel register */
1811  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1812  PRU_SUART_CH_CONFIG2_OFFSET;
1813  pru_ram_read_data(offset, (Uint8 *) & u32DataLen, 2, &pru_arm_iomap);
1814 
1815  /* read the character length */
1816  u32CharLen = u32DataLen & PRU_SUART_CH_CONFIG2_BITPERCHAR_MASK;
1817  u32CharLen -= 2; /* remove the START & STOP bit */
1818 
1819  u32DataLen &= PRU_SUART_CH_CONFIG2_DATALEN_MASK;
1820  u32DataLen = u32DataLen >> PRU_SUART_CH_CONFIG2_DATALEN_SHIFT;
1821  u32DataLen ++;
1822 
1823  /* if the character length is greater than 8, then the size doubles */
1824  if (u32CharLen > 8)
1825  {
1826  u32DataLen *= 2;
1827  }
1828 
1829  /* Check if the time-out had occured. If, yes, then we need to find the
1830  * number of bytes read from PRU. Else, we need to read the requested bytes
1831  */
1832  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1833  PRU_SUART_CH_TXRXSTATUS_OFFSET;
1834  pru_ram_read_data(offset, (Uint8 *) & u16Status, 1, &pru_arm_iomap);
1835 
1836  if (u16Status & CHN_TXRX_STATUS_TIMEOUT)
1837  {
1838  /* determine the number of bytes read into the FIFO */
1839  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1840  PRU_SUART_CH_BYTESDONECNTR_OFFSET;
1841 
1842  pru_ram_read_data(offset, (Uint8 *) & u32DataRead, 1, &pru_arm_iomap);
1843 
1844  /* if the character length is greater than 8, then the size doubles */
1845  if (u32CharLen > 8)
1846  {
1847  u32DataRead *= 2;
1848  }
1849 
1850  /* the data corresponding is loaded in second half during the timeout */
1851  if (u32DataRead > u32DataLen)
1852  {
1853  u32DataRead -= u32DataLen;
1854  pu8SrcAddr += u32DataLen;
1855  }
1856 
1857  pru_softuart_clrRxFifo (hUart);
1858  }
1859  else
1860  {
1861  u32DataRead = u32DataLen;
1862  /* Determine the buffer index by reading the FIFO_OddEven flag*/
1863  if (u16Status & CHN_TXRX_STATUS_CMPLT)
1864  {
1865  /* if the bit is set, the data is in the first half of the FIFO else
1866  * the data is in the second half
1867  */
1868  pu8SrcAddr += u32DataLen;
1869  }
1870  }
1871 
1872  /* we should be copying only max len given by the application */
1873  if (u32DataRead > s32MaxLen)
1874  {
1875  u32DataRead = s32MaxLen;
1876  }
1877 
1878  /* evaluate the virtual address of the FIFO address based on the physical addr */
1879  pu8SrcAddr = (Uint8 *) ((Uint32) pu8SrcAddr - (Uint32) pru_arm_iomap.pFifoBufferPhysBase +
1880  (Uint32) pru_arm_iomap.pFifoBufferVirtBase);
1881 
1882  /* Now we have both the data length and the source address. copy */
1883  for (offset = 0; offset < u32DataRead; offset++)
1884  {
1885  * pDataBuffer++ = * pu8SrcAddr++;
1886  }
1887  * pu32DataRead = u32DataRead;
1888 
1889  retVal = PRU_SUART_SUCCESS;
1890 
1891  return (retVal);
1892 }
1893 
1894 /*
1895  * suart routine to disable the receive functionality. This routine stops the PRU
1896  * from receiving on selected UART and also disables the McASP serializer corresponding
1897  * to this UART Rx line.
1898  */
1899 short pru_softuart_stopReceive (suart_handle hUart)
1900 {
1901  unsigned short status = SUART_SUCCESS;
1902  unsigned int offset;
1903  unsigned int pruOffset;
1904  unsigned short chNum;
1905  unsigned short u16Status;
1906 
1907  if (hUart == NULL) {
1908  return (PRU_SUART_ERR_HANDLE_INVALID);
1909  }
1910 
1911  chNum = hUart->uartNum - 1;
1912  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1913  {
1914 
1915  /* channel starts from 0 and uart instance starts from 1 */
1916  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1917 
1918  if (hUart->uartNum <= 4)
1919  {
1920  /* PRU0 */
1921  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1922  } else {
1923  /* PRU1 */
1924  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1925  /* First 8 channel corresponds to PRU0 */
1926  chNum -= 8;
1927  }
1928  chNum++;
1929  }
1930  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
1931  {
1932  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1933  }
1934  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
1935  {
1936  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1937  }
1938  else
1939  {
1940  return PRU_MODE_INVALID;
1941  }
1942 
1943  /* read the existing value of status flag */
1944  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1945  PRU_SUART_CH_TXRXSTATUS_OFFSET;
1946  pru_ram_read_data(offset, (Uint8 *) &u16Status, 1, &pru_arm_iomap);
1947 
1948  /* we need to clear the busy bit corresponding to this receive channel */
1949  u16Status &= ~(CHN_TXRX_STATUS_RDY);
1950  pru_ram_write_data(offset, (Uint8 *) & u16Status, 1, &pru_arm_iomap);
1951 
1952  /* get the serizlizer number being used for this Rx channel */
1953  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
1954  PRU_SUART_CH_CTRL_OFFSET;
1955  pru_ram_read_data(offset, (Uint8 *) &u16Status, 2, &pru_arm_iomap);
1956  u16Status &= PRU_SUART_CH_CTRL_SR_MASK;
1957  u16Status = u16Status >> PRU_SUART_CH_CTRL_SR_SHIFT;
1958 
1959  /* we need to de-activate the serializer corresponding to this receive */
1960  status = suart_asp_serializer_deactivate (u16Status, &pru_arm_iomap);
1961 
1962  return (status);
1963 
1964 }
1965 
1966 /*
1967  * suart routine to get the tx status for a specific uart
1968  */
1969 short pru_softuart_getTxStatus(suart_handle hUart)
1970 {
1971  unsigned int offset;
1972  unsigned int pruOffset;
1973  unsigned short status = SUART_SUCCESS;
1974  unsigned short chNum;
1975 
1976  if (hUart == NULL) {
1977  return (PRU_SUART_ERR_HANDLE_INVALID);
1978  }
1979 
1980  chNum = hUart->uartNum - 1 ;
1981  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
1982  {
1983  /* channel starts from 0 and uart instance starts from 1 */
1984  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
1985 
1986 
1987  if (hUart->uartNum <= 4)
1988  {
1989  /* PRU0 */
1990  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
1991  } else {
1992  /* PRU1 */
1993  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
1994  /* First 8 channel corresponds to PRU0 */
1995  chNum -= 8;
1996  }
1997  }
1998  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
1999  {
2000  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2001  }
2002  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
2003  {
2004  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2005  }
2006  else
2007  {
2008  return PRU_MODE_INVALID;
2009  }
2010 
2011  offset =
2012  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2013  PRU_SUART_CH_TXRXSTATUS_OFFSET;
2014  pru_ram_read_data(offset, (Uint8 *) & status, 1, &pru_arm_iomap);
2015  return (status);
2016 }
2017 
2018 short pru_softuart_clrTxStatus(suart_handle hUart)
2019 {
2020  unsigned int offset;
2021  unsigned int pruOffset;
2022  unsigned short status = SUART_SUCCESS;
2023  unsigned short chNum;
2024 
2025  if (hUart == NULL) {
2026  return (PRU_SUART_ERR_HANDLE_INVALID);
2027  }
2028 
2029  chNum = hUart->uartNum - 1 ;
2030 
2031  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2032  {
2033 
2034  /* channel starts from 0 and uart instance starts from 1 */
2035  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2036 
2037  if (hUart->uartNum <= 4)
2038  {
2039  /* PRU0 */
2040  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2041  } else {
2042  /* PRU1 */
2043  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2044  /* First 8 channel corresponds to PRU0 */
2045  chNum -= 8;
2046  }
2047  }
2048  else if (PRU0_MODE == PRU_MODE_TX_ONLY )
2049  {
2050  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2051  }
2052  else if (PRU1_MODE == PRU_MODE_TX_ONLY)
2053  {
2054  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2055  }
2056  else
2057  {
2058  return PRU_MODE_INVALID;
2059  }
2060 
2061  offset =
2062  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2063  PRU_SUART_CH_TXRXSTATUS_OFFSET;
2064  pru_ram_read_data(offset, (Uint8 *) & status, 1, &pru_arm_iomap);
2065 
2066  status &= ~(0x2);
2067  pru_ram_write_data(offset, (Uint8 *) & status, 1, &pru_arm_iomap);
2068  return (status);
2069 }
2070 
2071 /*
2072  * suart routine to get the rx status for a specific uart
2073  */
2074 short pru_softuart_getRxStatus(suart_handle hUart)
2075 {
2076  unsigned int offset;
2077  unsigned int pruOffset;
2078  unsigned short status = SUART_SUCCESS;
2079  unsigned short chNum;
2080 
2081  if (hUart == NULL) {
2082  return (PRU_SUART_ERR_HANDLE_INVALID);
2083  }
2084 
2085  chNum = hUart->uartNum - 1 ;
2086  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2087  {
2088  /* channel starts from 0 and uart instance starts from 1 */
2089  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2090 
2091  if (hUart->uartNum <= 4)
2092  {
2093  /* PRU0 */
2094  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2095  } else {
2096  /* PRU1 */
2097  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2098  /* First 8 channel corresponds to PRU0 */
2099  chNum -= 8;
2100  }
2101  chNum++;
2102  }
2103  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
2104  {
2105  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2106  }
2107  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
2108  {
2109  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2110  }
2111  else
2112  {
2113  return PRU_MODE_INVALID;
2114  }
2115 
2116  offset =
2117  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2118  PRU_SUART_CH_TXRXSTATUS_OFFSET;
2119  pru_ram_read_data(offset, (Uint8 *) &status, 1, &pru_arm_iomap);
2120  return (status);
2121 }
2122 
2123 short pru_softuart_clrRxFifo(suart_handle hUart)
2124 {
2125  unsigned int offset;
2126  unsigned int pruOffset;
2127  unsigned short status = SUART_SUCCESS;
2128  unsigned short chNum;
2129  unsigned short regVal;
2130  unsigned short uartNum;
2131 
2132  if (hUart == NULL) {
2133  return (PRU_SUART_ERR_HANDLE_INVALID);
2134  }
2135 
2136  uartNum = hUart->uartNum;
2137 
2138  chNum = hUart->uartNum - 1;
2139 
2140  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2141  {
2142 
2143  /* channel starts from 0 and uart instance starts from 1 */
2144  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2145 
2146  if (hUart->uartNum <= 4)
2147  {
2148  /* PRU0 */
2149  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2150  } else {
2151  /* PRU1 */
2152  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2153  /* First 8 channel corresponds to PRU0 */
2154  chNum -= 8;
2155  }
2156  chNum++;
2157  }
2158  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
2159  {
2160  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2161  uartNum = 0;
2162  }
2163  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
2164  {
2165  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2166  uartNum = 1;
2167  }
2168  else
2169  {
2170  return PRU_MODE_INVALID;
2171  }
2172 
2173  /* Reset the number of bytes read into the FIFO */
2174  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2175  PRU_SUART_CH_BYTESDONECNTR_OFFSET;
2176 
2177  pru_ram_read_data(offset, (Uint8 *) & regVal, 1, &pru_arm_iomap);
2178  regVal &= 0x00;
2179 
2180  pru_ram_write_data(offset, (Uint8 *) & regVal, 1, &pru_arm_iomap);
2181 
2182  /* Service Request to PRU */
2183  offset = pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2184  PRU_SUART_CH_CTRL_OFFSET;
2185 
2186  pru_ram_read_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
2187 
2188  regVal &= ~(PRU_SUART_CH_CTRL_MODE_MASK |PRU_SUART_CH_CTRL_SREQ_MASK);
2189 
2190  regVal |= ( PRU_SUART_CH_CTRL_RX_MODE << PRU_SUART_CH_CTRL_MODE_SHIFT) |
2191  (PRU_SUART_CH_CTRL_SREQ << PRU_SUART_CH_CTRL_SREQ_SHIFT);
2192 
2193  pru_ram_write_data(offset, (Uint8 *) & regVal, 2, &pru_arm_iomap);
2194  suart_intr_setmask (hUart->uartNum, PRU_RX_INTR, CHN_TXRX_IE_MASK_TIMEOUT);
2195 
2196  /* generate ARM->PRU event */
2197  suart_arm_to_pru_intr(uartNum);
2198 
2199  return (status);
2200 }
2201 
2202 
2203 short pru_softuart_clrRxStatus(suart_handle hUart)
2204 {
2205  unsigned int offset;
2206  unsigned int pruOffset;
2207  unsigned short status = SUART_SUCCESS;
2208  unsigned short chNum;
2209 
2210  if (hUart == NULL) {
2211  return (PRU_SUART_ERR_HANDLE_INVALID);
2212  }
2213 
2214  chNum = hUart->uartNum - 1;
2215  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2216  {
2217 
2218  /* channel starts from 0 and uart instance starts from 1 */
2219  chNum = (hUart->uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2220 
2221  if (hUart->uartNum <= 4)
2222  {
2223  /* PRU0 */
2224  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2225  } else {
2226  /* PRU1 */
2227  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2228  /* First 8 channel corresponds to PRU0 */
2229  chNum -= 8;
2230  }
2231  chNum++;
2232  }
2233  else if (PRU0_MODE == PRU_MODE_RX_ONLY )
2234  {
2235  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2236  }
2237  else if (PRU1_MODE == PRU_MODE_RX_ONLY)
2238  {
2239  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2240  }
2241  else
2242  {
2243  return PRU_MODE_INVALID;
2244  }
2245 
2246  offset =
2247  pruOffset + (chNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2248  PRU_SUART_CH_TXRXSTATUS_OFFSET;
2249  pru_ram_read_data(offset, (Uint8 *) & status, 1, &pru_arm_iomap);
2250 
2251  status &= ~(0x3C);
2252  pru_ram_write_data(offset, (Uint8 *) & status, 1, &pru_arm_iomap);
2253  return (status);
2254 }
2255 
2256 /*
2257  * suart_intr_status_read: Gets the Global Interrupt status register
2258  * for the specified SUART.
2259  * uartNum < 1 to 6 >
2260  * txrxFlag < Indicates TX or RX interrupt for the uart >
2261  */
2262 short pru_softuart_get_isrstatus(unsigned short uartNum, unsigned short *txrxFlag)
2263 {
2264  unsigned int u32IntcOffset;
2265  unsigned int chNum = 0xFF;
2266  unsigned int regVal = 0;
2267  unsigned int u32RegVal = 0;
2268  unsigned int u32ISRValue = 0;
2269  unsigned int u32AckRegVal = 0;
2270  unsigned int u32StatInxClrRegoffset = 0;
2271 
2272  /* initialize the status & Flag to known value */
2273  *txrxFlag = 0;
2274 
2275  u32StatInxClrRegoffset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATIDXCLR &
2276  0xFFFF);
2277 
2278  /* Read PRU Interrupt Status Register from PRU */
2279  u32IntcOffset =
2280  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATCLRINT1 &
2281  0xFFFF);
2282 
2283  pru_ram_read_data_4byte(u32IntcOffset, (unsigned int *)&u32ISRValue, 1);
2284 
2285  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2286  {
2287  /* channel starts from 0 and uart instance starts from 1 */
2288  chNum = uartNum * 2 - 2;
2289 
2290  /* Check if the interrupt occured for Tx */
2291  u32RegVal = PRU_SUART0_TX_EVT_BIT << ((uartNum - 1)* 2);
2292  if (u32ISRValue & u32RegVal)
2293  {
2294  /* interupt occured for TX */
2295  *txrxFlag |= PRU_TX_INTR;
2296 
2297  /* acknowledge the TX interrupt */
2298  u32AckRegVal = chNum + PRU_SUART0_TX_EVT;
2299  pru_ram_write_data_4byte(u32StatInxClrRegoffset, (unsigned int *)&u32AckRegVal, 1);
2300 
2301  }
2302 
2303  /* Check if the interrupt occured for Rx */
2304  u32RegVal = PRU_SUART0_RX_EVT_BIT << ((uartNum - 1)* 2);
2305  pru_ram_read_data_4byte(u32IntcOffset, (unsigned int *)&u32ISRValue, 1);
2306  if (u32ISRValue & u32RegVal)
2307  {
2308  /* interupt occured for RX */
2309  *txrxFlag |= PRU_RX_INTR;
2310  chNum += 1;
2311 
2312  /* acknowledge the RX interrupt */
2313  u32AckRegVal = chNum + PRU_SUART0_TX_EVT;
2314  pru_ram_write_data_4byte(u32StatInxClrRegoffset, (unsigned int *)&u32AckRegVal, 1);
2315  }
2316  }
2317  else
2318  {
2319  chNum = uartNum - 1;
2320  if ((u32ISRValue & 0x03FC) != 0)
2321  {
2322  /* PRU0 */
2323  u32RegVal = 1 << (uartNum + 1);
2324  if (u32ISRValue & u32RegVal)
2325  {
2326  /* acknowledge the interrupt */
2327  u32AckRegVal = chNum + PRU_SUART0_TX_EVT;
2328  pru_ram_write_data_4byte(u32StatInxClrRegoffset, (unsigned int *)&u32AckRegVal, 1);
2329  *txrxFlag |= PRU_RX_INTR;
2330  }
2331  }
2332 
2333  pru_ram_read_data_4byte(u32IntcOffset, (unsigned int *)&u32ISRValue, 1);
2334  if (u32ISRValue & 0x3FC00)
2335  {
2336  /* PRU1 */
2337  u32RegVal = 1 << (uartNum + 9);
2338  if (u32ISRValue & u32RegVal)
2339  {
2340  /* acknowledge the interrupt */
2341  u32AckRegVal = chNum + PRU_SUART4_TX_EVT;
2342  pru_ram_write_data_4byte(u32StatInxClrRegoffset, (unsigned int *)&u32AckRegVal, 1);
2343  *txrxFlag |= PRU_TX_INTR;
2344  }
2345  }
2346 
2347  }
2348 
2349  return regVal;
2350 }
2351 
2352 int pru_intr_clr_isrstatus(unsigned short uartNum, unsigned int txrxmode)
2353 {
2354  unsigned int offset;
2355  unsigned short txrxFlag = 0;
2356  unsigned short chnNum;
2357 
2358  chnNum = uartNum - 1;
2359  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2360  {
2361  /* channel starts from 0 and uart instance starts from 1 */
2362  chnNum = (uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2363 
2364  if (uartNum <= 4)
2365  {
2366  /* PRU0 */
2367  offset = PRU_SUART_PRU0_ISR_OFFSET + 1;
2368  } else {
2369  /* PRU1 */
2370  offset = PRU_SUART_PRU1_ISR_OFFSET + 1;
2371  /* First 8 channel corresponds to PRU0 */
2372  chnNum -= 8;
2373  }
2374 
2375  if (2 == txrxmode)
2376  chnNum++;
2377  }
2378  else if (PRU0_MODE == txrxmode)
2379  {
2380  offset = PRU_SUART_PRU0_ISR_OFFSET + 1;
2381  }
2382  else if (PRU1_MODE == txrxmode)
2383  {
2384  offset = PRU_SUART_PRU1_ISR_OFFSET + 1;
2385  }
2386  else
2387  {
2388  return PRU_MODE_INVALID;
2389  }
2390 
2391  pru_ram_read_data(offset, (Uint8 *) & txrxFlag, 1, &pru_arm_iomap);
2392  txrxFlag &= ~(0x2);
2393  pru_ram_write_data(offset, (Uint8 *) & txrxFlag, 1, &pru_arm_iomap);
2394 
2395  return 0;
2396 }
2397 
2398 short suart_arm_to_pru_intr(unsigned short uartNum)
2399 {
2400  unsigned int u32offset;
2401  unsigned int u32value;
2402  short s16retval;
2403 
2404  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2405  {
2406  if ((uartNum > 0) && (uartNum <= 4)) {
2407  /* PRU0 SYS_EVT32 */
2408  u32value = 0x20;
2409  } else if ((uartNum > 4) && (uartNum <= 8)) {
2410  /* PRU1 SYS_EVT33 */
2411  u32value = 0x21;
2412  } else {
2413  return SUART_INVALID_UART_NUM;
2414  }
2415  }
2416 
2417  if ((PRU0_MODE == PRU_MODE_RX_ONLY) || (PRU1_MODE == PRU_MODE_RX_ONLY) ||
2418  (PRU0_MODE == PRU_MODE_TX_ONLY) || (PRU1_MODE == PRU_MODE_TX_ONLY))
2419  {
2420  if (uartNum == PRU_NUM0)
2421  {
2422  /* PRU0 SYS_EVT32 */
2423  u32value = 0x20;
2424  }
2425 
2426  if (uartNum == PRU_NUM1)
2427  {
2428  /* PRU0 SYS_EVT33 */
2429  u32value = 0x21;
2430  }
2431  }
2432 
2433  u32offset =
2434  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATIDXSET &
2435  0xFFFF);
2436  s16retval =
2437  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2438  if (s16retval == -1) {
2439  return -1;
2440  }
2441  return 0;
2442 }
2443 
2444 short arm_to_pru_intr_init(void)
2445 {
2446  unsigned int u32offset;
2447  unsigned int u32value;
2448  unsigned int intOffset;
2449  short s16retval = -1;
2450 #if 0
2451  /* Set the MCASP Event to PRU0 as Edge Triggered */
2452  u32offset =
2453  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_TYPE0&
2454  0xFFFF);
2455  u32value = 0x80000000;
2456  s16retval =
2457  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2458  if (s16retval == -1) {
2459  return -1;
2460  }
2461 #endif
2462  /* Clear all the host interrupts */
2463  for (intOffset = 0; intOffset <= PRU_INTC_HOSTINTLVL_MAX; intOffset++)
2464  {
2465  u32offset =
2466  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HSTINTENIDXCLR&
2467  0xFFFF);
2468  u32value = intOffset;
2469  s16retval =
2470  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2471  if (s16retval == -1) {
2472  return -1;
2473  }
2474  }
2475 
2476  /* Enable the global interrupt */
2477  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_GLBLEN &
2478  0xFFFF);
2479  u32value = 0x1;
2480  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2481  if (s16retval == -1) {
2482  return -1;
2483  }
2484 
2485  /* Enable the Host interrupts for all host channels */
2486  for (intOffset = 0; intOffset <=PRU_INTC_HOSTINTLVL_MAX; intOffset++)
2487  {
2488  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HSTINTENIDXSET &
2489  0xFFFF);
2490  u32value = intOffset;
2491  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2492  if (s16retval == -1) {
2493  return -1;
2494  }
2495  }
2496 
2497  /* host to channel mapping : Setting the host interrupt for channels 0,1,2,3 */
2498  u32offset =
2499  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HOSTMAP0 &
2500  0xFFFF);
2501  u32value = 0x03020100;
2502  s16retval =
2503  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2504  if (-1 == s16retval) {
2505  return -1;
2506  }
2507 
2508  /* host to channel mapping : Setting the host interrupt for channels 4,5,6,7 */
2509  u32offset =
2510  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HOSTMAP1 &
2511  0xFFFF);
2512  u32value = 0x07060504;
2513  s16retval =
2514  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2515  if (-1 == s16retval) {
2516  return -1;
2517  }
2518 
2519  /* host to channel mapping : Setting the host interrupt for channels 8,9 */
2520  u32offset =
2521  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HOSTMAP2 &
2522  0xFFFF);
2523  u32value = 0x00000908;
2524  s16retval =
2525  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2526  if (-1 == s16retval) {
2527  return -1;
2528  }
2529 
2530  /* Set the channel for System intrrupts
2531  * MAP Channel 0 to SYS_EVT31
2532  */
2533  u32offset =
2534  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP7 &
2535  0xFFFF);
2536  u32value = 0x0000000000;
2537  s16retval =
2538  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2539  if (-1 == s16retval) {
2540  return -1;
2541  }
2542 
2543 
2544  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2545  {
2546  /* Sets the channel for the system interrupt
2547  * MAP channel 0 to SYS_EVT32
2548  * MAP channel 1 to SYS_EVT33
2549  * MAP channel 2 to SYS_EVT34 SUART0-Tx
2550  * MAP channel 2 to SYS_EVT35 SUART0-Rx
2551  */
2552  u32offset =
2553  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP8 &
2554  0xFFFF);
2555  u32value = 0x02020100;
2556  s16retval =
2557  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2558  if (-1 == s16retval) {
2559  return -1;
2560  }
2561 
2562  /* Sets the channel for the system interrupt
2563  * MAP channel 3 to SYS_EVT36 SUART1-Tx
2564  * MAP channel 3 to SYS_EVT37 SUART1-Rx
2565  * MAP channel 4 to SYS_EVT38 SUART2-Tx
2566  * MAP channel 4 to SYS_EVT39 SUART2-Rx
2567  */
2568  u32offset =
2569  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP9 &
2570  0xFFFF);
2571  u32value = 0x04040303;
2572  s16retval =
2573  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2574  if (-1 == s16retval) {
2575  return -1;
2576  }
2577 
2578  /* Sets the channel for the system interrupt
2579  * MAP channel 5 to SYS_EVT40 SUART3-Tx
2580  * MAP channel 5 to SYS_EVT41 SUART3-Rx
2581  * MAP channel 6 to SYS_EVT42 SUART4-Tx
2582  * MAP channel 6 to SYS_EVT43 SUART4-Rx
2583  */
2584  u32offset =
2585  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP10 &
2586  0xFFFF);
2587  u32value = 0x06060505;
2588  s16retval =
2589  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2590  if (-1 == s16retval) {
2591  return -1;
2592  }
2593 
2594  /* Sets the channel for the system interrupt
2595  * MAP channel 7 to SYS_EVT44 SUART5-Tx
2596  * MAP channel 7 to SYS_EVT45 SUART5-Rx
2597  * MAP channel 8 to SYS_EVT46 SUART6-Tx
2598  * MAP channel 8 to SYS_EVT47 SUART6-Rx
2599  */
2600  u32offset =
2601  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP11 &
2602  0xFFFF);
2603  u32value = 0x08080707;
2604  s16retval =
2605  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2606  if (-1 == s16retval) {
2607  return -1;
2608  }
2609 
2610  /* Sets the channel for the system interrupt
2611  * MAP channel 9 to SYS_EVT48 SUART7-Tx
2612  * MAP channel 9 to SYS_EVT49 SUART7-Rx
2613  * MAP Channel 1 to SYS_EVT50
2614  */
2615  u32offset =
2616  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP12 &
2617  0xFFFF);
2618  u32value = 0x00010909;
2619  s16retval =
2620  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2621  if (-1 == s16retval) {
2622  return -1;
2623  }
2624  }
2625 
2626  if ((PRU0_MODE == PRU_MODE_RX_ONLY) || (PRU1_MODE == PRU_MODE_RX_ONLY) ||
2627  (PRU0_MODE == PRU_MODE_TX_ONLY) || (PRU1_MODE == PRU_MODE_TX_ONLY))
2628  {
2629  /* Sets the channel for the system interrupt
2630  * MAP channel 0 to SYS_EVT32
2631  * MAP channel 1 to SYS_EVT33
2632  * MAP channel 2 to SYS_EVT34 SUART0
2633  * MAP channel 3 to SYS_EVT35 SUART1
2634  */
2635  u32offset =
2636  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP8 &
2637  0xFFFF);
2638  u32value = 0x03020100;
2639  s16retval =
2640  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2641  if (-1 == s16retval) {
2642  return -1;
2643  }
2644 
2645  /* Sets the channel for the system interrupt
2646  * MAP channel 4 to SYS_EVT36 SUART2
2647  * MAP channel 5 to SYS_EVT37 SUART3
2648  * MAP channel 6 to SYS_EVT38 SUART4
2649  * MAP channel 7 to SYS_EVT39 SUART5
2650  */
2651  u32offset =
2652  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP9 &
2653  0xFFFF);
2654  u32value = 0x07060504;
2655  s16retval =
2656  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2657  if (-1 == s16retval) {
2658  return -1;
2659  }
2660 
2661  /* Sets the channel for the system interrupt
2662  * MAP channel 8 to SYS_EVT40 SUART6
2663  * MAP channel 9 to SYS_EVT41 SUART7
2664  * MAP channel 2 to SYS_EVT42 SUART0
2665  * MAP channel 3 to SYS_EVT43 SUART1
2666  */
2667  u32offset =
2668  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP10 &
2669  0xFFFF);
2670  u32value = 0x03020908;
2671  s16retval =
2672  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2673  if (-1 == s16retval) {
2674  return -1;
2675  }
2676 
2677  /* Sets the channel for the system interrupt
2678  * MAP channel 4 to SYS_EVT44 SUART2
2679  * MAP channel 5 to SYS_EVT45 SUART3
2680  * MAP channel 6 to SYS_EVT46 SUART4
2681  * MAP channel 7 to SYS_EVT47 SUART5
2682  */
2683  u32offset =
2684  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP11 &
2685  0xFFFF);
2686  u32value = 0x07060504;
2687  s16retval =
2688  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2689  if (-1 == s16retval) {
2690  return -1;
2691  }
2692 
2693  /* Sets the channel for the system interrupt
2694  * MAP channel 8 to SYS_EVT48 SUART6
2695  * MAP channel 9 to SYS_EVT49 SUART7
2696  * MAP Channel 1 to SYS_EVT50 PRU to PRU Intr
2697  */
2698  u32offset =
2699  (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_CHANMAP12 &
2700  0xFFFF);
2701  u32value = 0x00010908;
2702  s16retval =
2703  pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2704  if (-1 == s16retval) {
2705  return -1;
2706  }
2707  }
2708 
2709  /* Clear required set of system events and enable them using indexed register */
2710  for (intOffset = 0; intOffset < 18; intOffset++)
2711  {
2712  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_STATIDXCLR & 0xFFFF);
2713  u32value = 32 + intOffset;
2714  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int *) &u32value, 1);
2715  if (s16retval == -1) {
2716  return -1;
2717  }
2718 
2719  }
2720  /* enable only the HOST to PRU interrupts and let the PRU to Host events be
2721  * enabled by the separate API on demand basis.
2722  */
2723  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXSET & 0xFFFF);
2724  u32value = 31;
2725  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2726  if (s16retval == -1) {
2727  return -1;
2728  }
2729  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXSET & 0xFFFF);
2730  u32value = 32;
2731  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2732  if (s16retval == -1) {
2733  return -1;
2734  }
2735  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXSET & 0xFFFF);
2736  u32value = 33;
2737  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2738  if (s16retval == -1) {
2739  return -1;
2740  }
2741  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXSET & 0xFFFF);
2742  u32value = 50;
2743  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2744  if (s16retval == -1) {
2745  return -1;
2746  }
2747 
2748  /* Enable the global interrupt */
2749  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_GLBLEN &
2750  0xFFFF);
2751  u32value = 0x1;
2752  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2753  if (s16retval == -1) {
2754  return -1;
2755  }
2756 
2757  /* Enable the Host interrupts for all host channels */
2758  for (intOffset = 0; intOffset <=PRU_INTC_HOSTINTLVL_MAX; intOffset++)
2759  {
2760  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_HSTINTENIDXSET &
2761  0xFFFF);
2762  u32value = intOffset;
2763  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int *)&u32value, 1);
2764  if (s16retval == -1) {
2765  return -1;
2766  }
2767  }
2768 
2769  return 0;
2770 }
2771 
2772 int suart_pru_to_host_intr_enable (unsigned short uartNum,
2773  unsigned int txrxmode, int s32Flag)
2774 {
2775  int retVal = 0;
2776  unsigned int u32offset;
2777  unsigned int chnNum;
2778  unsigned int u32value;
2779  short s16retval = 0;
2780 
2781  if (uartNum > 8) {
2782  return SUART_INVALID_UART_NUM;
2783  }
2784 
2785  chnNum = uartNum - 1;
2786  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2787  {
2788  chnNum = (uartNum * 2) - 2;
2789  if (2 == txrxmode) { /* Rx mode */
2790  chnNum++;
2791  }
2792  u32value = 34 + chnNum;
2793  }
2794  else if ((PRU_MODE_RX_ONLY == txrxmode) && (PRU0_MODE == PRU_MODE_RX_ONLY))
2795  u32value = 34 + chnNum;
2796  else if ((PRU_MODE_RX_ONLY == txrxmode) && (PRU1_MODE == PRU_MODE_RX_ONLY))
2797  u32value = 42 + chnNum;
2798  else if ((PRU_MODE_TX_ONLY == txrxmode) && (PRU0_MODE == PRU_MODE_TX_ONLY))
2799  u32value = 34 + chnNum;
2800  else if ((PRU_MODE_TX_ONLY == txrxmode) && (PRU1_MODE == PRU_MODE_TX_ONLY))
2801  u32value = 42 + chnNum;
2802  else
2803  return -1;
2804 
2805  if (TRUE == s32Flag)
2806  {
2807  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXSET & 0xFFFF);
2808  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2809  if (s16retval == -1) {
2810  return -1;
2811  }
2812  }
2813  else
2814  {
2815  u32offset = (unsigned int)pru_arm_iomap.pru_io_addr | (PRU_INTC_ENIDXCLR & 0xFFFF);
2816  s16retval = pru_ram_write_data_4byte(u32offset, (unsigned int*) &u32value, 1);
2817  if (s16retval == -1) {
2818  return -1;
2819  }
2820  }
2821  return (retVal);
2822 }
2823 
2824 int suart_intr_setmask(unsigned short uartNum,
2825  unsigned int txrxmode, unsigned int intrmask)
2826 {
2827  unsigned int offset;
2828  unsigned int pruOffset;
2829  unsigned int txrxFlag;
2830  unsigned int regval = 0;
2831  unsigned int chnNum;
2832 
2833  chnNum = uartNum -1;
2834  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2835  {
2836  /* channel starts from 0 and uart instance starts from 1 */
2837  chnNum = (uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2838 
2839  if ((uartNum > 0) && (uartNum <= 4)) {
2840 
2841  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2842  offset = PRU_SUART_PRU0_IMR_OFFSET;
2843  } else if ((uartNum > 4) && (uartNum <= 8)) {
2844  /* PRU1 */
2845  offset = PRU_SUART_PRU1_IMR_OFFSET;
2846  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2847  /* First 8 channel corresponds to PRU0 */
2848  chnNum -= 8;
2849  } else {
2850  return SUART_INVALID_UART_NUM;
2851  }
2852 
2853  if (2 == txrxmode) { /* rx mode */
2854  chnNum++;
2855  }
2856  }
2857  else if (PRU0_MODE == txrxmode)
2858  {
2859  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2860  offset = PRU_SUART_PRU0_IMR_OFFSET;
2861  }
2862  else if (PRU1_MODE == txrxmode)
2863  {
2864  offset = PRU_SUART_PRU1_IMR_OFFSET;
2865  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2866  }
2867  else
2868  {
2869  return PRU_MODE_INVALID;
2870  }
2871 
2872 
2873  regval = 1 << chnNum;
2874 
2875  if (CHN_TXRX_IE_MASK_CMPLT == (intrmask & CHN_TXRX_IE_MASK_CMPLT))
2876  {
2877  pru_ram_read_data(offset, (Uint8 *) & txrxFlag, 2,
2878  &pru_arm_iomap);
2879  txrxFlag &= ~(regval);
2880  txrxFlag |= regval;
2881  pru_ram_write_data(offset, (Uint8 *) & txrxFlag, 2,
2882  &pru_arm_iomap);
2883  }
2884 
2885  if ((intrmask & SUART_GBL_INTR_ERR_MASK) == SUART_GBL_INTR_ERR_MASK) {
2886  regval = 0;
2887  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
2888  &pru_arm_iomap);
2889  regval &= ~(SUART_GBL_INTR_ERR_MASK);
2890  regval |= (SUART_GBL_INTR_ERR_MASK);
2891  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
2892  &pru_arm_iomap);
2893 
2894  }
2895  /* Break Indicator Interrupt Masked */
2896  if ((intrmask & CHN_TXRX_IE_MASK_FE) == CHN_TXRX_IE_MASK_FE) {
2897  regval = 0;
2898  offset =
2899  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2900  PRU_SUART_CH_CONFIG1_OFFSET;
2901  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
2902  &pru_arm_iomap);
2903  regval &= ~(CHN_TXRX_IE_MASK_FE);
2904  regval |= CHN_TXRX_IE_MASK_FE;
2905  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
2906  &pru_arm_iomap);
2907  }
2908  /* Framing Error Interrupt Masked */
2909  if (CHN_TXRX_IE_MASK_BI == (intrmask & CHN_TXRX_IE_MASK_BI)) {
2910  regval = 0;
2911  offset =
2912  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2913  PRU_SUART_CH_CONFIG1_OFFSET;
2914 
2915  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
2916  &pru_arm_iomap);
2917  regval &= ~(CHN_TXRX_IE_MASK_BI);
2918  regval |= CHN_TXRX_IE_MASK_BI;
2919  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
2920  &pru_arm_iomap);
2921  }
2922  /* Timeout error Interrupt Masked */
2923  if (CHN_TXRX_IE_MASK_TIMEOUT == (intrmask & CHN_TXRX_IE_MASK_TIMEOUT)) {
2924  regval = 0;
2925  offset =
2926  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2927  PRU_SUART_CH_CONFIG1_OFFSET;
2928 
2929  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
2930  &pru_arm_iomap);
2931  regval &= ~(CHN_TXRX_IE_MASK_TIMEOUT);
2932  regval |= CHN_TXRX_IE_MASK_TIMEOUT;
2933  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
2934  &pru_arm_iomap);
2935  }
2936  /* Overrun error Interrupt Masked */
2937  if (CHN_RX_IE_MASK_OVRN == (intrmask & CHN_RX_IE_MASK_OVRN)) {
2938  regval = 0;
2939  offset =
2940  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
2941  PRU_SUART_CH_CONFIG1_OFFSET;
2942 
2943  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
2944  &pru_arm_iomap);
2945  regval &= ~(CHN_RX_IE_MASK_OVRN);
2946  regval |= CHN_RX_IE_MASK_OVRN;
2947  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
2948  &pru_arm_iomap);
2949  }
2950  return 0;
2951 }
2952 
2953 int suart_intr_clrmask(unsigned short uartNum,
2954  unsigned int txrxmode, unsigned int intrmask)
2955 {
2956  unsigned int offset;
2957  unsigned int pruOffset;
2958  unsigned short txrxFlag;
2959  unsigned short regval = 0;
2960  unsigned short chnNum;
2961 
2962  chnNum = uartNum -1;
2963  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
2964  {
2965  /* channel starts from 0 and uart instance starts from 1 */
2966  chnNum = (uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
2967 
2968  if ((uartNum > 0) && (uartNum <= 4)) {
2969 
2970  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2971  offset = PRU_SUART_PRU0_IMR_OFFSET;
2972  } else if ((uartNum > 4) && (uartNum <= 8)) {
2973  /* PRU1 */
2974  offset = PRU_SUART_PRU1_IMR_OFFSET;
2975  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2976  /* First 8 channel corresponds to PRU0 */
2977  chnNum -= 8;
2978  } else {
2979  return SUART_INVALID_UART_NUM;
2980  }
2981 
2982  if (2 == txrxmode) { /* rx mode */
2983  chnNum++;
2984  }
2985  }
2986  else if (PRU0_MODE == txrxmode)
2987  {
2988  pruOffset = PRU_SUART_PRU0_CH0_OFFSET;
2989  offset = PRU_SUART_PRU0_IMR_OFFSET;
2990  }
2991  else if (PRU1_MODE == txrxmode)
2992  {
2993  offset = PRU_SUART_PRU1_IMR_OFFSET;
2994  pruOffset = PRU_SUART_PRU1_CH0_OFFSET;
2995  }
2996  else
2997  {
2998  return PRU_MODE_INVALID;
2999  }
3000 
3001  regval = 1 << chnNum;
3002 
3003  if (CHN_TXRX_IE_MASK_CMPLT == (intrmask & CHN_TXRX_IE_MASK_CMPLT)) {
3004  pru_ram_read_data(offset, (Uint8 *) & txrxFlag, 2,
3005  &pru_arm_iomap);
3006  txrxFlag &= ~(regval);
3007  pru_ram_write_data(offset, (Uint8 *) & txrxFlag, 2,
3008  &pru_arm_iomap);
3009  }
3010 
3011  if ((intrmask & SUART_GBL_INTR_ERR_MASK) == SUART_GBL_INTR_ERR_MASK) {
3012  regval = 0;
3013  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
3014  &pru_arm_iomap);
3015  regval &= ~(SUART_GBL_INTR_ERR_MASK);
3016  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
3017  &pru_arm_iomap);
3018 
3019  }
3020  /* Break Indicator Interrupt Masked */
3021  if ((intrmask & CHN_TXRX_IE_MASK_FE) == CHN_TXRX_IE_MASK_FE) {
3022  regval = 0;
3023  offset =
3024  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
3025  PRU_SUART_CH_CONFIG1_OFFSET;
3026  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
3027  &pru_arm_iomap);
3028  regval &= ~(CHN_TXRX_IE_MASK_FE);
3029  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
3030  &pru_arm_iomap);
3031  }
3032  /* Framing Error Interrupt Masked */
3033  if (CHN_TXRX_IE_MASK_BI == (intrmask & CHN_TXRX_IE_MASK_BI)) {
3034  regval = 0;
3035  offset =
3036  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
3037  PRU_SUART_CH_CONFIG1_OFFSET;
3038 
3039  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
3040  &pru_arm_iomap);
3041  regval &= ~(CHN_TXRX_IE_MASK_BI);
3042  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
3043  &pru_arm_iomap);
3044  }
3045 
3046  /* Timeout error Interrupt Masked */
3047  if (CHN_TXRX_IE_MASK_TIMEOUT == (intrmask & CHN_TXRX_IE_MASK_TIMEOUT)) {
3048  regval = 0;
3049  offset =
3050  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
3051  PRU_SUART_CH_CONFIG1_OFFSET;
3052 
3053  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
3054  &pru_arm_iomap);
3055  regval &= ~(CHN_TXRX_IE_MASK_TIMEOUT);
3056  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
3057  &pru_arm_iomap);
3058  }
3059  /* Overrun error Interrupt Masked */
3060  if (CHN_RX_IE_MASK_OVRN == (intrmask & CHN_RX_IE_MASK_OVRN)) {
3061  regval = 0;
3062  offset =
3063  pruOffset + (chnNum * SUART_NUM_OF_BYTES_PER_CHANNEL) +
3064  PRU_SUART_CH_CONFIG1_OFFSET;
3065 
3066  pru_ram_read_data(offset, (Uint8 *) & regval, 2,
3067  &pru_arm_iomap);
3068  regval &= ~(CHN_RX_IE_MASK_OVRN);
3069  pru_ram_write_data(offset, (Uint8 *) & regval, 2,
3070  &pru_arm_iomap);
3071  }
3072  return 0;
3073 }
3074 
3075 int suart_intr_getmask(unsigned short uartNum,
3076  unsigned int txrxmode, unsigned int intrmask)
3077 {
3078  unsigned short chnNum;
3079  unsigned int offset;
3080  unsigned short txrxFlag;
3081  unsigned short regval = 1;
3082 
3083  chnNum = uartNum -1;
3084  if ((PRU0_MODE == PRU_MODE_RX_TX_BOTH) || (PRU1_MODE == PRU_MODE_RX_TX_BOTH))
3085  {
3086  /* channel starts from 0 and uart instance starts from 1 */
3087  chnNum = (uartNum * SUART_NUM_OF_CHANNELS_PER_SUART) - 2;
3088 
3089  if ((uartNum > 0) && (uartNum <= 4)) {
3090 
3091  offset = PRU_SUART_PRU0_IMR_OFFSET;
3092  } else if ((uartNum > 4) && (uartNum <= 8)) {
3093  /* PRU1 */
3094  offset = PRU_SUART_PRU1_IMR_OFFSET;
3095  /* First 8 channel corresponds to PRU0 */
3096  chnNum -= 8;
3097  } else {
3098  return SUART_INVALID_UART_NUM;
3099  }
3100 
3101  if (2 == txrxmode) { /* rx mode */
3102  chnNum++;
3103  }
3104  }
3105  else if (PRU0_MODE == txrxmode)
3106  {
3107  offset = PRU_SUART_PRU0_IMR_OFFSET;
3108  }
3109  else if (PRU1_MODE == txrxmode)
3110  {
3111  offset = PRU_SUART_PRU1_IMR_OFFSET;
3112  }
3113  else
3114  {
3115  return PRU_MODE_INVALID;
3116  }
3117 
3118  regval = regval << chnNum;
3119 
3120  pru_ram_read_data(offset, (Uint8 *) & txrxFlag, 2, &pru_arm_iomap);
3121  txrxFlag &= regval;
3122  if (0 == intrmask) {
3123  if (txrxFlag == 0)
3124  return 1;
3125  }
3126 
3127  if (1 == intrmask) {
3128  if (txrxFlag == regval)
3129  return 1;
3130  }
3131  return 0;
3132 }
3133 
3134 static int suart_set_pru_id (unsigned int pru_no)
3135 {
3136  unsigned int offset;
3137  unsigned short reg_val = 0;
3138 
3139  if (0 == pru_no)
3140  {
3141  offset = PRU_SUART_PRU0_ID_ADDR;
3142  }
3143  else if (1 == pru_no)
3144  {
3145  offset = PRU_SUART_PRU1_ID_ADDR;
3146  }
3147  else
3148  {
3149  return PRU_SUART_FAILURE;
3150  }
3151 
3152  pru_ram_read_data(offset, (Uint8 *) & reg_val, 1, &pru_arm_iomap);
3153  reg_val &=~SUART_PRU_ID_MASK;
3154  reg_val = pru_no;
3155  pru_ram_write_data(offset, (Uint8 *) & reg_val, 1, &pru_arm_iomap);
3156 
3157  return PRU_SUART_SUCCESS;
3158 }
3159 /* End of file */
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Definition: suart_api.c:1005
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One line description of the structure.
Definition: suart_api.h:394
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Definition: suart_pru_regs.h:134
PRU_SUART_CH_CTRL_MODE_SHIFT
#define PRU_SUART_CH_CTRL_MODE_SHIFT
Definition: suart_pru_regs.h:126
PRU_SUART2_CONFIG_TX_SER
#define PRU_SUART2_CONFIG_TX_SER
Definition: omapl_suart_board.h:32
ePRU_SUART_DATA_BITS12
Definition: suart_api.h:198
PRU_INTC_CHANMAP9
#define PRU_INTC_CHANMAP9
Definition: pru.h:65
PRU_SUART_SERIALIZER_NONE
#define PRU_SUART_SERIALIZER_NONE
Definition: suart_utils.h:66
PRU_SUART_CH_TXRXDATA_OFFSET
#define PRU_SUART_CH_TXRXDATA_OFFSET
Definition: suart_pru_regs.h:169
CHN_RX_IE_MASK_OVRN
#define CHN_RX_IE_MASK_OVRN
Definition: suart_api.h:69
suart_api.h
PRU_SUART_PRU0_CH0_OFFSET
#define PRU_SUART_PRU0_CH0_OFFSET
Definition: suart_pru_regs.h:53
suart_struct_handle::uartTxChannel
unsigned short uartTxChannel
Definition: suart_api.h:398
PRU_SUART_ERR_PARAMETER_INVALID
#define PRU_SUART_ERR_PARAMETER_INVALID
Definition: suart_err.h:39
PRU_SUART1_CONFIG_TX_SER
#define PRU_SUART1_CONFIG_TX_SER
Definition: omapl_suart_board.h:28
PRU_SUART_UART2
#define PRU_SUART_UART2
Definition: suart_api.h:127
PRU_SUART_CH_CONFIG1_OFFSET
#define PRU_SUART_CH_CONFIG1_OFFSET
Definition: suart_pru_regs.h:166
MCASP_XBUF_BASE_ADDR
#define MCASP_XBUF_BASE_ADDR
Definition: suart_api.h:114
MCASP_SRCTL_TX_MODE
#define MCASP_SRCTL_TX_MODE
Definition: suart_api.h:118
PRU_INTC_HOSTMAP1
#define PRU_INTC_HOSTMAP1
Definition: pru.h:73
suart_mcasp_config
void suart_mcasp_config(unsigned int mcasp_addr, unsigned int txBaudValue, unsigned int rxBaudValue, unsigned int oversampling, arm_pru_iomap *pru_arm_iomap)
Definition: suart_utils.c:154
pru_softuart_deinit
short pru_softuart_deinit(void)
Definition: suart_api.c:689
pru_softuart_pending_tx_request
int pru_softuart_pending_tx_request(void)
Definition: suart_api.c:1530
pru_run
__FAR__ Uint32 pru_run(Uint8 pruNum, arm_pru_iomap *pru_arm_iomap)
Definition: pru.c:58
PRU_SUART_PRU1_ID_ADDR
#define PRU_SUART_PRU1_ID_ADDR
Definition: suart_pru_regs.h:115
PRU_SUART_UARTx_INVALID
#define PRU_SUART_UARTx_INVALID
Definition: suart_api.h:143
PRU_SUART_PRU0_ISR_OFFSET
#define PRU_SUART_PRU0_ISR_OFFSET
Definition: suart_pru_regs.h:73
PRU_SUART4_CONFIG_TX_SER
#define PRU_SUART4_CONFIG_TX_SER
Definition: omapl_suart_board.h:41
pru_suart_tx_cntx_priv::buff_addr
unsigned short buff_addr
Definition: suart_api.h:354
PRU_SUART_CH_CTRL_SR_MASK
#define PRU_SUART_CH_CTRL_SR_MASK
Definition: suart_pru_regs.h:141
pru_softuart_init
short pru_softuart_init(unsigned int txBaudValue, unsigned int rxBaudValue, unsigned int oversampling, unsigned char *pru_suart_emu_code, unsigned int fw_size, arm_pru_iomap *arm_iomap_pru)
Definition: suart_api.c:530
PRU_SUART_CH_CONFIG2_BITPERCHAR_MASK
#define PRU_SUART_CH_CONFIG2_BITPERCHAR_MASK
Definition: suart_pru_regs.h:155
PRU_SUART8_CONFIG_TX_SER
#define PRU_SUART8_CONFIG_TX_SER
Definition: omapl_suart_board.h:58
PRU_INTC_HOSTINTLVL_MAX
#define PRU_INTC_HOSTINTLVL_MAX
Definition: pru.h:102
SUART_CHN_ENABLED
Definition: suart_api.h:176
pru_softuart_setbaud
short pru_softuart_setbaud(suart_handle hUart, unsigned short txClkDivisor, unsigned short rxClkDivisor)
Definition: suart_api.c:894
PRU_TX_INTR
#define PRU_TX_INTR
Definition: suart_api.h:57
suart_pru_regs.h
pru_softuart_read
short pru_softuart_read(suart_handle hUart, unsigned int *ptDataBuf, unsigned short dataLen)
Definition: suart_api.c:1664
PRU_INTC_HSTINTENIDXCLR
#define PRU_INTC_HSTINTENIDXCLR
Definition: pru.h:46
suart_intr_clrmask
int suart_intr_clrmask(unsigned short uartNum, unsigned int txrxmode, unsigned int intrmask)
Definition: suart_api.c:2953
pru_suart_rx_cntx_priv::asp_rsrctl_base
unsigned int asp_rsrctl_base
Definition: suart_api.h:362
PRU_SUART0_TX_EVT
#define PRU_SUART0_TX_EVT
Definition: suart_pru_regs.h:173
PRU_SUART3_CONFIG_DUPLEX
#define PRU_SUART3_CONFIG_DUPLEX
Definition: omapl_suart_board.h:35
PRU_SUART_CH_CONFIG1_OVS_MASK
#define PRU_SUART_CH_CONFIG1_OVS_MASK
Definition: suart_pru_regs.h:150
suart_struct_handle::uartRxChannel
unsigned short uartRxChannel
Definition: suart_api.h:400
SUART_UART_IN_USE
#define SUART_UART_IN_USE
Definition: suart_err.h:67
PRU_INTC_ENIDXSET
#define PRU_INTC_ENIDXSET
Definition: pru.h:43
PRU_SUART_FAILURE
#define PRU_SUART_FAILURE
Definition: suart_err.h:28
PRU1_MODE
#define PRU1_MODE
Definition: suart_api.h:100
SUART_DEFAULT_OVRSMPL
#define SUART_DEFAULT_OVRSMPL
Definition: suart_api.h:82
arm_pru_iomap::syscfg_io_addr
void * syscfg_io_addr
Definition: pru.h:115
pru_softuart_setconfig
short pru_softuart_setconfig(suart_handle hUart, suart_config *configUart)
Definition: suart_api.c:1112
PRU_SUART7_CONFIG_RX_SER
#define PRU_SUART7_CONFIG_RX_SER
Definition: omapl_suart_board.h:53
arm_pru_iomap
Definition: pru.h:110
RX_DEFAULT_DATA_DUMP_ADDR
#define RX_DEFAULT_DATA_DUMP_ADDR
Definition: suart_api.h:122
CHN_TXRX_STATUS_CMPLT
#define CHN_TXRX_STATUS_CMPLT
Definition: suart_api.h:66
ePRU_SUART_UART_FREE
Definition: suart_api.h:293
CHN_TXRX_IE_MASK_FE
#define CHN_TXRX_IE_MASK_FE
Definition: suart_api.h:72
suart_config
One line description of the structure.
Definition: suart_api.h:375
suart_mcasp_psc_enable
void suart_mcasp_psc_enable(unsigned int psc1_addr)
Definition: suart_utils.c:426
arm_pru_iomap::pru_io_addr
void * pru_io_addr
Definition: pru.h:111
PRU_SUART_SUCCESS
#define PRU_SUART_SUCCESS
Definition: suart_err.h:26
suart_err.h
pru_ram_write_data_4byte
short pru_ram_write_data_4byte(unsigned int u32offset, unsigned int *pu32datatoread, short u16wordstoread)
pru_ram_write_data_4byte() Download the data into data RAM of PRU0 or PRU1 of OMAP L138...
Definition: pru.c:278
PRU_INTC_TYPE0
#define PRU_INTC_TYPE0
Definition: pru.h:87
pru_softuart_getRxStatus
short pru_softuart_getRxStatus(suart_handle hUart)
Definition: suart_api.c:2074
PRU_SUART5_CONFIG_TX_SER
#define PRU_SUART5_CONFIG_TX_SER
Definition: omapl_suart_board.h:46
PRU_SUART_CH_CTRL_OFFSET
#define PRU_SUART_CH_CTRL_OFFSET
Definition: suart_pru_regs.h:165
pru_softuart_getTxDataLen
short pru_softuart_getTxDataLen(suart_handle hUart)
Definition: suart_api.c:1286
PRU_SUART0_RX_EVT_BIT
#define PRU_SUART0_RX_EVT_BIT
Definition: suart_pru_regs.h:191
PRU_SUART_CH_CTRL_SR_SHIFT
#define PRU_SUART_CH_CTRL_SR_SHIFT
Definition: suart_pru_regs.h:140
PRU_SUART7_CONFIG_TX_SER
#define PRU_SUART7_CONFIG_TX_SER
Definition: omapl_suart_board.h:54
suart_config::txBitsPerChar
unsigned char txBitsPerChar
Definition: suart_api.h:382
suart_intr_getmask
int suart_intr_getmask(unsigned short uartNum, unsigned int txrxmode, unsigned int intrmask)
Definition: suart_api.c:3075
suart_config::TXSerializer
unsigned char TXSerializer
Definition: suart_api.h:376
PRU_NUM1
#define PRU_NUM1
Definition: pru.h:19
arm_pru_iomap::pFifoBufferVirtBase
void * pFifoBufferVirtBase
Definition: pru.h:117
PRU_SUART_CH_CTRL_SREQ_MASK
#define PRU_SUART_CH_CTRL_SREQ_MASK
Definition: suart_pru_regs.h:133
PRU_SUART_CH_TXRXSTATUS_OFFSET
#define PRU_SUART_CH_TXRXSTATUS_OFFSET
Definition: suart_pru_regs.h:168
cslr_mcasp.h
PRU_SUART_UART7
#define PRU_SUART_UART7
Definition: suart_api.h:138
PRU_SUART1_CONFIG_DUPLEX
#define PRU_SUART1_CONFIG_DUPLEX
Definition: omapl_suart_board.h:26
PRU_INTC_CHANMAP8
#define PRU_INTC_CHANMAP8
Definition: pru.h:64
SUART_INVALID_UART_NUM
#define SUART_INVALID_UART_NUM
Definition: suart_err.h:70
PRU_INTC_ENIDXCLR
#define PRU_INTC_ENIDXCLR
Definition: pru.h:44
suart_struct_handle::uartStatus
unsigned short uartStatus
Definition: suart_api.h:402
suart_asp_serializer_deactivate
short suart_asp_serializer_deactivate(unsigned short u16srNum, arm_pru_iomap *pru_arm_iomap)
Definition: suart_utils.c:392
pru_softuart_get_isrstatus
short pru_softuart_get_isrstatus(unsigned short uartNum, unsigned short *txrxFlag)
Definition: suart_api.c:2262
suart_mcasp_reset
void suart_mcasp_reset(arm_pru_iomap *pru_arm_iomap)
Definition: suart_utils.c:140
PRU_SUART_CH_CONFIG2_BITPERCHAR_SHIFT
#define PRU_SUART_CH_CONFIG2_BITPERCHAR_SHIFT
Definition: suart_pru_regs.h:154
PRU_SUART_CH_CTRL_RX_MODE
#define PRU_SUART_CH_CTRL_RX_MODE
Definition: suart_pru_regs.h:129
PRU_SUART_CH_CONFIG2_DATALEN_MASK
#define PRU_SUART_CH_CONFIG2_DATALEN_MASK
Definition: suart_pru_regs.h:159
SUART_PRU_ID_MASK
#define SUART_PRU_ID_MASK
Definition: suart_api.h:76
PRU_INTC_CHANMAP12
#define PRU_INTC_CHANMAP12
Definition: pru.h:68
pru_softuart_close
short pru_softuart_close(suart_handle hUart)
Definition: suart_api.c:875
PRU_SUART_ERR_HANDLE_INVALID
#define PRU_SUART_ERR_HANDLE_INVALID
Definition: suart_err.h:37
PRU_SUART_CH_CTRL_TX_MODE
#define PRU_SUART_CH_CTRL_TX_MODE
Definition: suart_pru_regs.h:128
PRU_INTC_CHANMAP7
#define PRU_INTC_CHANMAP7
Definition: pru.h:63
pru_softuart_getconfig
short pru_softuart_getconfig(suart_handle hUart, suart_config *configUart)
Definition: suart_api.c:1401
PRU_MODE_INVALID
#define PRU_MODE_INVALID
Definition: suart_api.h:90
pru_suart_rx_cntx_priv::asp_rbuf_base
unsigned int asp_rbuf_base
Definition: suart_api.h:361
NULL
#define NULL
Definition: pru_can_emulation_api.h:37