LMS 2012
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d_uart_mod.c
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1 /*
2  * LEGO® MINDSTORMS EV3
3  *
4  * Copyright (C) 2010-2013 The LEGO Group
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19  */
20 
21 
51 #define LOWEST_BITRATE 2400 // Lowest possible bit rate (always used for sync and info) [b/S]
52 #define MIDLE_BITRATE 57600 // Highest bit rate allowed when adjusting clock [b/S]
53 #define HIGHEST_BITRATE 460800 // Highest possible bit rate [b/S]
54 
55 #define MIDLE_BITRATE_DEVIATION 40 // Largest deviation able to adjust clock to [%]
56 #define MIDLE_BITRATE_INCREAMENT 1 // Amount to adjust per loop [%]
57 #define MIDLE_BITRATE_FIX 5 // Last adjustment to get in the middle of the bit [%]
58 
59 /*
60  SEQUENCE WHEN UART DEVICE IS DETECTED
61  =====================================
62 
63  HOST DEVICE
64  ------------------------------------------------------------ ----------------------------------------------------------------------
65  - Reset <----------------------------,
66  - Set TX active (low) |
67  - Set RX floating |
68  - Wait half a second 1st.time (next time >=10mS) |
69  |
70  - Enable UART communication - Enable UART communication |
71  - Setup UART for LOWEST_BITRATE - Setup UART for LOWEST_BITRATE |
72  - Setup hardware buffers |
73  |
74  |
75  - Sync clocks - Sync clocks (only used on no XTAL devices) |
76  - Wait for receive of byte <-. <-- SYNC - Send sync pulse <------------. |
77  - If CMD is received skip to send INFO | | |
78  - Check byte against SYNC | | |
79  - If not SYNC increase UART clock --' - Timeout 5mS (UART byte time) --' |
80  - Send sync feedback SYNC --> - Receive sync pulse |
81  |
82  |
83  - Exchange informations - Exchange informations |
84  - Receive command data <-- CMD - Send command data (type,modes,speed, etc) |
85  - Send command data (type,modes,speed, etc) CMD --> - Receive command data |
86  - Receive info data <-- INFO - Send info data (name,scaling,data format, etc) |
87  - Send info data (name,scaling,data format, etc) INFO --> - Receive info data |
88  - Receive acknowledge <-- ACK - When finished info send acknowledge |
89  - Timeout (80mS) -----------------------------'
90  - When finished info send acknowledge ACK --> - Receive acknowledge
91  - Switch to valid communication speed - Switch to valid communication speed
92 
93 
94  - Communication running - Communication running
95  - Receive data <-- DATA - Send data
96  - If out of sync, send not acknowledge NACK --> - If not acknowledge, repeat send data
97  - Receive data <-- DATA - Send data
98  - Receive data <-- DATA - Send data
99  - Receive data <-- DATA - Send data
100  --
101  - Send data DATA --> - Receive data
102  - Receive data <-- DATA - Send data
103  - Receive data <-- DATA - Send data
104  --
105  - Send command CMD --> - Receive command
106  - Receive data <-- DATA - Send data
107  - Receive data <-- DATA - Send data
108  --
109  - Send data DATA --> - Receive data
110  - If not acknowledge, repeat send data <-- NACK - If out of sync, send not acknowledge
111  - Send data DATA --> - Receive data
112  --
113 
114 
115  DEVICES WITH XTAL
116  =================
117 
118  Devices with a bit rate accuracy better that +-2% must start on LOWEST_BITRATE and skip the synchronisation sequence and just begin to send INFO.
119 
120  When placed wrong on an output port device TX should continue to transmit SYNC, INFO or DATA to ensure that the host detects
121  that connection 6 is low
122  \endverbatim
123  \ref ExampleUartProtocol "Ex."
124  \verbatim
125 
126 
127  DEVICES WITHOUT XTAL
128  ====================
129 
130  It is possible to use the power of the host to adjust to LOWEST_BITRATE if the device is not capable of meeting accuracy
131  of the bit rate. The adjustment factor is then used when switching to higher speeds up to MIDLE_BITRATE.
132 
133  These devices must start with a bit rate at LOWEST_BITRATE + worst case deviation from LOWEST_BITRATE
134 
135  When placed wrong on an output port device TX should continue to transmit SYNC, INFO or DATA to ensure that the host detects
136  that connection 6 is low
137 
138 
139 
140  DEVICES NOT ABLE TO RECEIVE
141  ===========================
142 
143  Devices that is not able to receive should send SYNC several times (MIDLE_BITRATE_DEVIATION / MIDLE_BITRATE_INCREAMENT + 1)
144 
145  When placed wrong on an output port device TX should continue to transmit SYNC, INFO or DATA to ensure that the host detects
146  that connection 6 is low
147 
148 
149 
150  HOST
151  ====
152 
153  The host should check every data message format against the info once sent from the device and send NACK if not valid
154 
155  UART devices is connected when system powers up!: the power to input/output ports is powered up when DCM driver is ready to evaluate the devices on
156  the ports (ensures that power up sync is executed when system is powered up)
157 
158 
159 
160  BIT RATE ADJUSTMENT
161  ===================
162 
163  I. Host starts with a bit rate at LOWEST_BITRATE
164 
165  II. Device must start with a bit rate at LOWEST_BITRATE + worst case deviation from LOWEST_BITRATE
166 
167  III. When the SYNC is received host will check it against the correct SYNC byte and if it is wrong the bit rate is raised MIDLE_BITRATE_INCREAMENT
168 
169  IV. If SYNC is received correctly the bit rate is raised additionally MIDLE_BITRATE_FIX and SYNC is sent to the device
170 
171  V. If info says that a higher bit rate is possible it is raised after transmitting ACK on the host and after receiving (or a time) ACK on the device
172  (if host has adjusted the bit rate the same factor will be used when raising)
173 
174 
175 \endverbatim
176  *
177  * \n
178  */
179 
180 
448 // FIRST BYTE
449 
450 #define BYTE_SYNC 0x00 // Synchronisation byte
451 #define BYTE_ACK 0x04 // Acknowledge byte
452 #define BYTE_NACK 0x02 // Not acknowledge byte
453 
454 #define MESSAGE_SYS 0x00 // System message
455 #define MESSAGE_CMD 0x40 // Command message
456 #define MESSAGE_INFO 0x80 // Info message
457 #define MESSAGE_DATA 0xC0 // Data message
458 #define GET_MESSAGE_TYPE(B) (B & 0xC0) // Get message type
459 
460 #define CMD_TYPE 0x00 // CMD command - TYPE (device type for VM reference)
461 #define CMD_MODES 0x01 // CMD command - MODES (number of supported modes 0=1)
462 #define CMD_SPEED 0x02 // CMD command - SPEED (maximun communication speed)
463 #define CMD_SELECT 0x03 // CMD command - SELECT (select mode)
464 #define CMD_WRITE 0x04 // CMD command - WRITE (write to device)
465 #define GET_CMD_COMMAND(B) (B & 0x07) // Get CMD command
466 
467 #define GET_MODE(B) (B & 0x07) // Get mode
468 
469 #define CONVERT_LENGTH(C) (1 << (C & 0x07))
470 #define GET_MESSAGE_LENGTH(B) (CONVERT_LENGTH(B >> 3)) // Get message length exclusive check byte
471 
472 #define MAKE_CMD_COMMAND(C,LC) (MESSAGE_CMD + (C & 0x07) + ((LC & 0x07) << 3))
473 
474 
475 // SECOND INFO BYTE
476 
477 #define INFO_NAME 0x00 // INFO command - NAME (device name)
478 #define INFO_RAW 0x01 // INFO command - RAW (device RAW value span)
479 #define INFO_PCT 0x02 // INFO command - PCT (device PCT value span)
480 #define INFO_SI 0x03 // INFO command - SI (device SI value span)
481 #define INFO_SYMBOL 0x04 // INFO command - SYMBOL (device SI unit symbol)
482 #define INFO_FORMAT 0x80 // INFO command - FORMAT (device data sets and format)
483 #define GET_INFO_COMMAND(B) (B) // Get INFO command
484 
485 
486 #ifndef PCASM
487 #include <asm/types.h>
488 #endif
489 
490 #define HW_ID_SUPPORT
491 
492 #include "../../lms2012/source/lms2012.h"
493 #include "../../lms2012/source/am1808.h"
494 
495 
496 TYPES TypeDefaultUart[] =
497 {
498 // Name Type Connection Mode DataSets Format Figures Decimals Views RawMin RawMax PctMin PctMax SiMin SiMax Time IdValue Pins Symbol
499  { "" , TYPE_UNKNOWN , CONN_UNKNOWN , 0 , 1 , 1 , 4 , 0 , 0 , 0.0, 1023.0, 0.0, 100.0, 0.0, 1023.0, 10, 0, '-', "" },
500  { "TERMINAL" , TYPE_TERMINAL , CONN_INPUT_UART , 0 , 0 , 0 , 4 , 0 , 0 , 0.0, 4095.0, 0.0, 100.0, 0.0, 1000.0, 0, 0, '-', "" },
501  { "\0" }
502 };
503 
504 
505 #ifdef DEBUG
506 #define DEBUG_D_UART
507 #endif
508 
509 
510 #ifdef DEBUG_D_UART
511 #define DEBUG
512 #define HIGHDEBUG
513 #define DEBUG_TRACE_MODE_CHANGE
514 #define DEBUG_D_UART_ERROR
515 #endif
516 
517 
518 #define MODULE_NAME "uart_module"
519 #define DEVICE1_NAME UART_DEVICE
520 #define DEVICE2_NAME TEST_UART_DEVICE
521 
522 static int ModuleInit(void);
523 static void ModuleExit(void);
524 
525 #include <linux/kernel.h>
526 #include <linux/fs.h>
527 
528 #include <linux/sched.h>
529 
530 #ifndef PCASM
531 #include <linux/mm.h>
532 #include <linux/hrtimer.h>
533 #include <linux/interrupt.h>
534 
535 #include <linux/init.h>
536 #include <linux/uaccess.h>
537 #include <linux/debugfs.h>
538 
539 #include <linux/ioport.h>
540 #include <asm/gpio.h>
541 #include <asm/io.h>
542 #include <linux/module.h>
543 #include <linux/miscdevice.h>
544 #include <asm/uaccess.h>
545 
546 
547 #ifndef DISABLE_PRU_UARTS
548 #include <linux/ti_omapl_pru_suart.h>
549 #include "omapl_suart_board.h"
550 #include "suart_api.h"
551 #include "suart_utils.h"
552 #include "suart_err.h"
553 #include "pru.h"
554 #include "lego_ti_omapl_pru_suart.h"
555 #endif
556 
557 MODULE_LICENSE("GPL");
558 MODULE_AUTHOR("The LEGO Group");
559 MODULE_DESCRIPTION(MODULE_NAME);
560 MODULE_SUPPORTED_DEVICE(DEVICE1_NAME);
561 
562 module_init(ModuleInit);
563 module_exit(ModuleExit);
564 
565 #else
566 // Keep Eclipse happy
567 #endif
568 
569 
570 int Hw = 0;
571 
572 #define NO_OF_INPUT_PORTS INPUTS
573 
574 enum InputUartPins
575 {
576  INPUT_UART_BUFFER,
577  INPUT_UART_TXD,
578  INPUT_UART_RXD,
579  INPUT_UART_PIN5,
580  INPUT_UART_PIN6,
581  INPUT_UART_PINS
582 };
583 
584 enum TestPins
585 {
586  TESTPIN,
587  TEST_PINS
588 };
589 
590 
591 INPIN InputUartPin[NO_OF_INPUT_PORTS][INPUT_UART_PINS];
592 
593 INPIN TestPin[TEST_PINS];
594 
595 
596 
597 #define Uart1 0
598 #define Uart2 1
599 #define Uart3 2
600 #define Uart4 3
601 
602 unsigned long UartBaseAddr[] =
603 {
604  0x01D0C000, // Port 1
605  0x01C42000, // Port 2
606  0, // Port 3
607  0 // Port 4
608 };
609 
610 
611 int UartIntr[] =
612 {
613  IRQ_DA8XX_UARTINT1, // Port 1
614  IRQ_DA8XX_UARTINT0, // Port 2
615  0, // Port 3
616  0 // Port 4
617 };
618 
619 
630 // EP2
631 
632 
633 INPIN EP2_InputUartPin[][INPUT_UART_PINS] =
634 {
635  { // Input UART 1
636  { GP8_11 , NULL, 0 }, // Buffer disable
637  { UART1_TXD , NULL, 0 }, // TXD
638  { UART1_RXD , NULL, 0 }, // RXD
639  { GP0_2 , NULL, 0 }, // Pin 5 - DIGIA0 - Digital input/output
640  { GP0_15 , NULL, 0 }, // Pin 6 - DIGIA1 - Digital input/output
641  },
642  { // Input UART 2
643  { GP8_14 , NULL, 0 }, // Buffer disable
644  { UART0_TXD , NULL, 0 }, // TXD
645  { UART0_RXD , NULL, 0 }, // RXD
646  { GP0_14 , NULL, 0 }, // Pin 5 - DIGIB0 - Digital input/output
647  { GP0_13 , NULL, 0 }, // Pin 6 - DIGIB1 - Digital input/output
648  },
649  { // Input UART 3
650  { GP7_9 , NULL, 0 }, // Buffer disable
651  { AXR4 , NULL, 0 }, // TXD
652  { -1 , NULL, 0 }, // RXD
653  { GP0_12 , NULL, 0 }, // Pin 5 - DIGIC0 - Digital input/output
654  { GP1_14 , NULL, 0 }, // Pin 6 - DIGIC1 - Digital input/output
655  },
656  { // Input UART 4
657  { GP7_10 , NULL, 0 }, // Buffer disable
658  { AXR3 , NULL, 0 }, // TXD
659  { -1 , NULL, 0 }, // RXD
660  { GP0_1 , NULL, 0 }, // Pin 5 - DIGID0 - Digital input/output
661  { GP1_15 , NULL, 0 }, // Pin 6 - DIGID1 - Digital input/output
662  },
663 };
664 
665 INPIN EP2_TestPin[TEST_PINS] =
666 {
667 #ifdef ENABLE_TEST_ON_PORT4
668  { GP1_15 , NULL, 0 } // PORT 4 PIN 6
669 #else
670  { GP2_7 , NULL, 0 } // TP4
671 #endif
672 };
673 
674 
675 // FINALB
676 
677 
678 INPIN FINALB_InputUartPin[][INPUT_UART_PINS] =
679 {
680  { // Input UART 1
681  { GP8_11 , NULL, 0 }, // Buffer disable
682  { UART1_TXD , NULL, 0 }, // TXD
683  { UART1_RXD , NULL, 0 }, // RXD
684  { GP0_2 , NULL, 0 }, // Pin 5 - DIGIA0 - Digital input/output
685  { GP0_15 , NULL, 0 }, // Pin 6 - DIGIA1 - Digital input/output
686  },
687  { // Input UART 2
688  { GP8_14 , NULL, 0 }, // Buffer disable
689  { UART0_TXD , NULL, 0 }, // TXD
690  { UART0_RXD , NULL, 0 }, // RXD
691  { GP0_14 , NULL, 0 }, // Pin 5 - DIGIB0 - Digital input/output
692  { GP0_13 , NULL, 0 }, // Pin 6 - DIGIB1 - Digital input/output
693  },
694  { // Input UART 3
695  { GP7_9 , NULL, 0 }, // Buffer disable
696  { AXR4 , NULL, 0 }, // TXD
697  { -1 , NULL, 0 }, // RXD
698  { GP0_12 , NULL, 0 }, // Pin 5 - DIGIC0 - Digital input/output
699  { GP1_14 , NULL, 0 }, // Pin 6 - DIGIC1 - Digital input/output
700  },
701  { // Input UART 4
702  { GP7_10 , NULL, 0 }, // Buffer disable
703  { AXR3 , NULL, 0 }, // TXD
704  { -1 , NULL, 0 }, // RXD
705  { GP1_13 , NULL, 0 }, // Pin 5 - DIGID0 - Digital input/output
706  { GP1_15 , NULL, 0 }, // Pin 6 - DIGID1 - Digital input/output
707  },
708 };
709 
710 INPIN FINALB_TestPin[TEST_PINS] =
711 {
712 #ifdef ENABLE_TEST_ON_PORT4
713  { GP1_15 , NULL, 0 } // PORT 4 PIN 6
714 #else
715  { GP2_7 , NULL, 0 } // TP4
716 #endif
717 };
718 
719 
720 // FINAL
721 
722 
723 INPIN FINAL_InputUartPin[][INPUT_UART_PINS] =
724 {
725  { // Input UART 1
726  { GP8_11 , NULL, 0 }, // Buffer disable
727  { UART1_TXD , NULL, 0 }, // TXD
728  { UART1_RXD , NULL, 0 }, // RXD
729  { GP0_2 , NULL, 0 }, // Pin 5 - DIGIA0 - Digital input/output
730  { GP0_15 , NULL, 0 }, // Pin 6 - DIGIA1 - Digital input/output
731  },
732  { // Input UART 2
733  { GP8_14 , NULL, 0 }, // Buffer disable
734  { UART0_TXD , NULL, 0 }, // TXD
735  { UART0_RXD , NULL, 0 }, // RXD
736  { GP0_14 , NULL, 0 }, // Pin 5 - DIGIB0 - Digital input/output
737  { GP0_13 , NULL, 0 }, // Pin 6 - DIGIB1 - Digital input/output
738  },
739  { // Input UART 3
740  { GP7_9 , NULL, 0 }, // Buffer disable
741  { -1 , NULL, 0 }, // TXD
742  { -1 , NULL, 0 }, // RXD
743  { GP0_12 , NULL, 0 }, // Pin 5 - DIGIC0 - Digital input/output
744  { GP1_14 , NULL, 0 }, // Pin 6 - DIGIC1 - Digital input/output
745  },
746  { // Input UART 4
747  { GP7_10 , NULL, 0 }, // Buffer disable
748  { -1 , NULL, 0 }, // TXD
749  { -1 , NULL, 0 }, // RXD
750  { GP1_13 , NULL, 0 }, // Pin 5 - DIGID0 - Digital input/output
751  { GP1_15 , NULL, 0 }, // Pin 6 - DIGID1 - Digital input/output
752  },
753 };
754 
755 
756 INPIN FINAL_TestPin[TEST_PINS] =
757 {
758 #ifdef ENABLE_TEST_ON_PORT4
759  { GP1_15 , NULL, 0 } // PORT 4 PIN 6
760 #else
761  { GP2_7 , NULL, 0 } // TP4
762 #endif
763 };
764 
765 
766 /* \endverbatim
767  * \n
768  */
769 
770 
771 INPIN *pInputUartPin[] =
772 {
773  [FINAL] = (INPIN*)&FINAL_InputUartPin[0], // FINAL platform
774  [FINALB] = (INPIN*)&FINALB_InputUartPin[0], // FINALB platform
775  [EP2] = (INPIN*)&EP2_InputUartPin[0], // EP2 platform
776 };
777 
778 
779 INPIN *pTestPin[] =
780 {
781  [FINAL] = FINAL_TestPin, // FINAL platform
782  [FINALB] = FINALB_TestPin, // FINALB platform
783  [EP2] = EP2_TestPin, // EP2 platform
784 };
785 
786 
787 //*****************************************************************************
788 
789 static void __iomem *GpioBase;
790 
791 
792 void SetGpio(int Pin)
793 {
794  int Tmp = 0;
795  void __iomem *Reg;
796 
797  if (Pin >= 0)
798  {
799  // unlock
800  REGUnlock;
801 
802  while ((MuxRegMap[Tmp].Pin != -1) && (MuxRegMap[Tmp].Pin != Pin))
803  {
804  Tmp++;
805  }
806  if (MuxRegMap[Tmp].Pin == Pin)
807  {
808  Reg = da8xx_syscfg0_base + 0x120 + (MuxRegMap[Tmp].MuxReg << 2);
809 
810  *(u32*)Reg &= MuxRegMap[Tmp].Mask;
811  *(u32*)Reg |= MuxRegMap[Tmp].Mode;
812 
813  if (Pin < NO_OF_GPIOS)
814  {
815 #ifdef DEBUG
816  printk(" GP%d_%-2d 0x%08X and 0x%08X or 0x%08X\n",(Pin >> 4),(Pin & 0x0F),(u32)Reg, MuxRegMap[Tmp].Mask, MuxRegMap[Tmp].Mode);
817 #endif
818  }
819  else
820  {
821 #ifdef DEBUG
822  printk(" FUNCTION 0x%08X and 0x%08X or 0x%08X\n",(u32)Reg, MuxRegMap[Tmp].Mask, MuxRegMap[Tmp].Mode);
823 #endif
824  }
825 
826  }
827  else
828  {
829  printk("* GP%d_%-2d ********* ERROR not found *********\n",(Pin >> 4),(Pin & 0x0F));
830  }
831 
832  // lock
833  REGLock;
834 
835  }
836 }
837 
838 
839 void InitGpio(void)
840 {
841  int Port;
842  int Pin;
843 
844 
845 #ifdef DEBUG
846  printk(" Uart\n");
847 #endif
848  memcpy(InputUartPin,pInputUartPin[Hw],sizeof(EP2_InputUartPin));
849  if (memcmp((const void*)InputUartPin,(const void*)pInputUartPin[Hw],sizeof(EP2_InputUartPin)) != 0)
850  {
851  printk("%s InputUartPin tabel broken!\n",MODULE_NAME);
852  }
853 
854  for (Port = 0;Port < INPUTS;Port++)
855  {
856 #ifdef DEBUG
857 // snprintf(UartBuffer,UARTBUFFERSIZE," UART on input port %d\n",Port + 1);
858 // UartWrite(UartBuffer);
859 #endif
860  for (Pin = 0;Pin < INPUT_UART_PINS;Pin++)
861  {
862  if (InputUartPin[Port][Pin].Pin >= 0)
863  {
864  InputUartPin[Port][Pin].pGpio = (struct gpio_controller *__iomem)(GpioBase + ((InputUartPin[Port][Pin].Pin >> 5) * 0x28) + 0x10);
865  InputUartPin[Port][Pin].Mask = (1 << (InputUartPin[Port][Pin].Pin & 0x1F));
866 
867  SetGpio(InputUartPin[Port][Pin].Pin);
868  }
869  }
870  }
871 
872 #ifdef DEBUG
873  printk(" Test\n");
874 #endif
875  memcpy(TestPin,pTestPin[Hw],sizeof(EP2_TestPin));
876  if (memcmp((const void*)TestPin,(const void*)pTestPin[Hw],sizeof(EP2_TestPin)) != 0)
877  {
878  printk("%s TestPin tabel broken!\n",MODULE_NAME);
879  }
880 
881  for (Pin = 0;Pin < TEST_PINS;Pin++)
882  {
883  if (TestPin[Pin].Pin >= 0)
884  {
885  TestPin[Pin].pGpio = (struct gpio_controller *__iomem)(GpioBase + ((TestPin[Pin].Pin >> 5) * 0x28) + 0x10);
886  TestPin[Pin].Mask = (1 << (TestPin[Pin].Pin & 0x1F));
887 
888  SetGpio(TestPin[Pin].Pin);
889  }
890  }
891 
892 
893 }
894 
895 
896 #define PUARTFloat(port,pin) {\
897  (*InputUartPin[port][pin].pGpio).dir |= InputUartPin[port][pin].Mask;\
898  }
899 
900 
901 #define PUARTRead(port,pin) ((*InputUartPin[port][pin].pGpio).in_data & InputUartPin[port][pin].Mask)
902 
903 
904 #define PUARTHigh(port,pin) {\
905  (*InputUartPin[port][pin].pGpio).set_data = InputUartPin[port][pin].Mask;\
906  (*InputUartPin[port][pin].pGpio).dir &= ~InputUartPin[port][pin].Mask;\
907  }
908 
909 #define PUARTLow(port,pin) {\
910  (*InputUartPin[port][pin].pGpio).clr_data = InputUartPin[port][pin].Mask;\
911  (*InputUartPin[port][pin].pGpio).dir &= ~InputUartPin[port][pin].Mask;\
912  }
913 
914 #define TESTOn {\
915  (*TestPin[TESTPIN].pGpio).set_data = TestPin[TESTPIN].Mask;\
916  (*TestPin[TESTPIN].pGpio).dir &= ~TestPin[TESTPIN].Mask;\
917  }
918 
919 #define TESTOff {\
920  (*TestPin[TESTPIN].pGpio).clr_data = TestPin[TESTPIN].Mask;\
921  (*TestPin[TESTPIN].pGpio).dir &= ~TestPin[TESTPIN].Mask;\
922  }
923 
924 
925 volatile ULONG *Base[INPUTS];
926 UBYTE IntSuccess[INPUTS];
927 #define UART_CLOCK1 132000000
928 #define UART_CLOCK2 150000000
929 // \todo UART clock 1 and 2 are different?
930 
931 #define UART_RBR 0
932 #define UART_THR 0
933 #define UART_IER 1
934 #define UART_IIR 2
935 #define UART_FCR 2
936 #define UART_LCR 3
937 #define UART_MCR 4
938 #define UART_LSR 5
939 #define UART_MSR 6
940 #define UART_SCR 7
941 #define UART_DLL 8
942 #define UART_DLH 9
943 #define UART_REVID1 10
944 #define UART_REVID2 11
945 #define UART_PWREMU_MGMT 12
946 #define UART_MDR 13
947 
948 #define UART_RECBUF_SIZE 256
949 
950 
951 #ifdef DEBUG_D_UART_ERROR
952 #define DEBUG_UART_WRITE
953 #endif
954 #ifdef DEBUG_TRACE_US
955 #define DEBUG_UART_WRITE
956 #endif
957 #ifdef DEBUG_TRACE_ANGLE
958 #define DEBUG_UART_WRITE
959 #endif
960 #ifdef DEBUG_TRACE_MODE_CHANGE
961 #define DEBUG_UART_WRITE
962 #endif
963 #ifdef DEBUG
964 #define DEBUG_UART_WRITE
965 #endif
966 #ifdef DEBUG_D_UART
967 #define DEBUG_UART_WRITE
968 #endif
969 
970 
971 #ifdef DEBUG_UART_WRITE
972 
973 #define UARTBUFFERSIZE 250
974 static char UartBuffer[UARTBUFFERSIZE];
975 //static void UartPortSetup(UBYTE Port,ULONG BitRate);
976 static UBYTE UartPortSend(UBYTE Port,UBYTE Byte);
977 
978 UWORD ShowTimer[INPUTS];
979 
980 #define LOGPOOLSIZE 100000
981 ULONG LogPointer = 0;
982 ULONG LogOutPointer = 0;
983 char LogPool[LOGPOOLSIZE];
984 
985 void UartWrite(char *pString)
986 {
987  ULONG Tmp;
988 
989  while (*pString)
990  {
991  LogPool[LogPointer] = *pString;
992 
993  Tmp = LogPointer;
994  Tmp++;
995  if (Tmp >= LOGPOOLSIZE)
996  {
997  Tmp = 0;
998  }
999  if (Tmp != LogOutPointer)
1000  {
1001  LogPointer = Tmp;
1002  pString++;
1003 
1004  }
1005  else
1006  {
1007 // if (UartPortSend(DEBUG_UART,*pString))
1008  {
1009  pString++;
1010  }
1011  }
1012  }
1013 }
1014 #endif
1015 
1016 
1017 // UART 1 *********************************************************************
1018 
1019 volatile ULONG *Uart1Base;
1020 static char Uart1Name[20];
1021 
1022 
1023 static UBYTE Uart1RecBuf[UART_RECBUF_SIZE];
1024 static UWORD Uart1RecBufIn;
1025 static UWORD Uart1RecBufOut;
1026 
1027 static UBYTE Uart1RecMesLng;
1028 static UBYTE Uart1RecMes[UART_BUFFER_SIZE];
1029 static UBYTE Uart1RecMesIn;
1030 
1031 
1032 irqreturn_t Uart1Interrupt(int irq, void *dev_id)
1033 {
1034  UBYTE IntrType;
1035 
1036  IntrType = (UBYTE)Uart1Base[UART_IIR] & 0x0F;
1037 
1038  while (!(IntrType & 1))
1039  {
1040  if (IntrType == 2)
1041  { // Transmitter ready
1042 
1043  }
1044  else
1045  { // Receiver ready
1046 
1047  if (IntrType & 2)
1048  { // Error - dummy read
1049 
1050  Uart1RecBuf[Uart1RecBufIn] = (UBYTE)Uart1Base[UART_LSR];
1051  }
1052  Uart1RecBuf[Uart1RecBufIn] = (UBYTE)Uart1Base[UART_RBR];
1053 
1054  if (++Uart1RecBufIn >= UART_RECBUF_SIZE)
1055  {
1056  Uart1RecBufIn = 0;
1057  }
1058 
1059  }
1060  IntrType = (UBYTE)Uart1Base[UART_IIR] & 0x0F;
1061  }
1062 
1063  return (IRQ_HANDLED);
1064 }
1065 
1066 
1067 static UBYTE Uart1Read(UBYTE *pByte)
1068 {
1069  UBYTE Result = 0;
1070 
1071  if (Uart1RecBufIn != Uart1RecBufOut)
1072  {
1073  *pByte = Uart1RecBuf[Uart1RecBufOut];
1074 
1075  if (++Uart1RecBufOut >= UART_RECBUF_SIZE)
1076  {
1077  Uart1RecBufOut = 0;
1078  }
1079  Result = 1;
1080  }
1081 
1082  return (Result);
1083 }
1084 
1085 
1086 static void Uart1Flush(void)
1087 {
1088  Uart1Base[UART_FCR] = 0x07;
1089  Uart1RecBufIn = 0;
1090  Uart1RecBufOut = 0;
1091  Uart1RecMesIn = 0;
1092 }
1093 
1094 
1095 static UBYTE Uart1ReadData(UBYTE *pCmd,UBYTE *pData,UBYTE *pCheck,UBYTE *pFail)
1096 {
1097  UBYTE Byte;
1098  UBYTE Length;
1099  UBYTE Collect;
1100 
1101  Length = 0;
1102  *pFail = 0xFF;
1103  Collect = 1;
1104 
1105  while (Collect)
1106  {
1107  if (Uart1Read(&Byte))
1108  {
1109  if (Uart1RecMesIn == 0)
1110  { // Wait for data message start
1111 
1112  if (GET_MESSAGE_TYPE(Byte) == MESSAGE_DATA)
1113  {
1114 
1115  Uart1RecMesLng = GET_MESSAGE_LENGTH(Byte) + 2;
1116 
1117  if (Uart1RecMesLng <= UART_BUFFER_SIZE)
1118  { // Valid length
1119 
1120  Uart1RecMes[Uart1RecMesIn] = Byte;
1121  Uart1RecMesIn++;
1122  }
1123  }
1124  }
1125  else
1126  {
1127  Uart1RecMes[Uart1RecMesIn] = Byte;
1128 
1129  if (++Uart1RecMesIn >= Uart1RecMesLng)
1130  { // Message ready
1131 
1132  *pCmd = Uart1RecMes[0];
1133  *pFail ^= *pCmd;
1134 
1135  while (Length < (Uart1RecMesLng - 2))
1136  {
1137  pData[Length] = Uart1RecMes[Length + 1];
1138  *pFail ^= pData[Length];
1139  Length++;
1140  }
1141  *pCheck = Uart1RecMes[Length + 1];
1142  *pFail ^= *pCheck;
1143 
1144  Uart1RecMesIn = 0;
1145  Collect = 0;
1146  }
1147  }
1148  }
1149  else
1150  {
1151  Collect = 0;
1152  }
1153  }
1154 
1155  return (Length);
1156 }
1157 
1158 
1159 static UBYTE Uart1Write(UBYTE Byte)
1160 {
1161  UBYTE Result = 0;
1162 
1163  if (Uart1Base[UART_LSR] & 0x20)
1164  {
1165  Uart1Base[UART_THR] = Byte;
1166  Result = 1;
1167  }
1168 
1169  return (Result);
1170 }
1171 
1172 
1173 static void Uart1Setup(ULONG BitRate)
1174 {
1175  ULONG Divisor;
1176 
1177  Divisor = (ULONG)UART_CLOCK1 / (BitRate * (ULONG)16);
1178  Uart1Base[UART_LCR] = 0x03;
1179  Uart1Base[UART_MDR] = 0x00;
1180  Uart1Base[UART_DLL] = Divisor & 0xFF;
1181  Uart1Base[UART_DLH] = (Divisor >> 8) & 0xFF;
1182 
1183  Uart1Base[UART_FCR] = 0x01;
1184  Uart1Base[UART_MCR] = 0x00;
1185 
1186 #ifndef UART1_FAKE_INTERRUPT
1187  Uart1Base[UART_IER] = 0x01;
1188 #else
1189  Uart1Base[UART_IER] = 0x00;
1190 #endif
1191 }
1192 
1193 
1194 
1195 #ifdef UART1_FAKE_INTERRUPT
1196 
1197 #define Uart1_RECEIVE_TIMER_RESOLUTION 500 // [uS]
1198 
1199 static struct hrtimer Uart1ReceiveTimer;
1200 static ktime_t Uart1ReceiveTime;
1201 
1202 
1203 static enum hrtimer_restart Uart1ReceiveInterruptFake(struct hrtimer *pTimer)
1204 {
1205  hrtimer_forward_now(pTimer,Uart1ReceiveTime);
1206 
1207  while (Uart1Base[UART_LSR] & 0x01)
1208  {
1209  Uart1RecBuf[Uart1RecBufIn] = (UBYTE)Uart1Base[UART_RBR];
1210 
1211  if (++Uart1RecBufIn >= UART_RECBUF_SIZE)
1212  {
1213  Uart1RecBufIn = 0;
1214  }
1215 
1216  }
1217 
1218  return (HRTIMER_RESTART);
1219 }
1220 #endif
1221 
1222 
1223 static int Uart1Init(void)
1224 {
1225  int Result = -1;
1226 
1227  Uart1Base = NULL;
1228  IntSuccess[Uart1] = 0;
1229  if (UartBaseAddr[Uart1])
1230  {
1231  // Base address defined
1232 
1233  snprintf(Uart1Name,20,"%s.port%d",DEVICE1_NAME,Uart1 + 1);
1234 
1235  if (request_mem_region(UartBaseAddr[Uart1],0x38,MODULE_NAME) >= 0)
1236  {
1237  // Map base address
1238 
1239  Uart1Base = (ULONG*)ioremap(UartBaseAddr[Uart1],0x38);
1240  Base[Uart1] = Uart1Base;
1241  if (Uart1Base != NULL)
1242  {
1243  // Map success
1244 #ifdef DEBUG
1245  printk(" %s memory mapped from 0x%08lX\r\n",DEVICE1_NAME,(unsigned long)Uart1Base);
1246 #endif
1247  Result = 0;
1248 #ifdef UART1_FAKE_INTERRUPT
1249  Uart1ReceiveTime = ktime_set(0,Uart1_RECEIVE_TIMER_RESOLUTION * 1000);
1250  hrtimer_init(&Uart1ReceiveTimer,CLOCK_MONOTONIC,HRTIMER_MODE_REL);
1251  Uart1ReceiveTimer.function = Uart1ReceiveInterruptFake;
1252  hrtimer_start(&Uart1ReceiveTimer,Uart1ReceiveTime,HRTIMER_MODE_REL);
1253 #endif
1254 
1255  if (request_irq(UartIntr[Uart1],&Uart1Interrupt,IRQF_SHARED,Uart1Name,&Uart1Name) >= 0)
1256  {
1257 #ifdef DEBUG
1258  printk(" %s request interrupt success for UART1\r\n",DEVICE1_NAME);
1259 #endif
1260  IntSuccess[Uart1] = 1;
1261  }
1262  else
1263  {
1264 #ifndef UART1_FAKE_INTERRUPT
1265  printk(" %s request interrupt failed for UART1\r\n",DEVICE1_NAME);
1266 #endif
1267  Result = -EBUSY;
1268  }
1269 
1270  }
1271  }
1272  }
1273 
1274  return (Result);
1275 }
1276 
1277 
1278 void Uart1Exit(void)
1279 {
1280 #ifndef UART1_FAKE_INTERRUPT
1281  Uart1Base[UART_IER] = 0x00;
1282 #else
1283  hrtimer_cancel(&Uart1ReceiveTimer);
1284 #endif
1285  if (Uart1Base != NULL)
1286  {
1287  if (IntSuccess[Uart1])
1288  {
1289  free_irq(UartIntr[Uart1],Uart1Name);
1290  }
1291  iounmap(Uart1Base);
1292  }
1293 }
1294 
1295 
1296 // UART 2 *********************************************************************
1297 
1298 volatile ULONG *Uart2Base;
1299 static char Uart2Name[20];
1300 
1301 
1302 
1303 
1304 static UBYTE Uart2RecBuf[UART_RECBUF_SIZE];
1305 static UWORD Uart2RecBufIn;
1306 static UWORD Uart2RecBufOut;
1307 
1308 static UBYTE Uart2RecMesLng;
1309 static UBYTE Uart2RecMes[UART_BUFFER_SIZE];
1310 static UBYTE Uart2RecMesIn;
1311 
1312 
1313 irqreturn_t Uart2Interrupt(int irq, void *dev_id)
1314 {
1315  UBYTE IntrType;
1316 
1317  IntrType = (UBYTE)Uart2Base[UART_IIR] & 0x0F;
1318 
1319  while (!(IntrType & 1))
1320  {
1321  if (IntrType == 2)
1322  { // Transmitter ready
1323 
1324  }
1325  else
1326  { // Receiver ready
1327 
1328  if (IntrType & 2)
1329  { // Error - dummy read
1330 
1331  Uart2RecBuf[Uart2RecBufIn] = (UBYTE)Uart2Base[UART_LSR];
1332  }
1333  Uart2RecBuf[Uart2RecBufIn] = (UBYTE)Uart2Base[UART_RBR];
1334 
1335  if (++Uart2RecBufIn >= UART_RECBUF_SIZE)
1336  {
1337  Uart2RecBufIn = 0;
1338  }
1339 
1340  }
1341  IntrType = (UBYTE)Uart2Base[UART_IIR] & 0x0F;
1342  }
1343 
1344  return (IRQ_HANDLED);
1345 }
1346 
1347 
1348 static UBYTE Uart2Read(UBYTE *pByte)
1349 {
1350  UBYTE Result = 0;
1351 
1352  if (Uart2RecBufIn != Uart2RecBufOut)
1353  {
1354  *pByte = Uart2RecBuf[Uart2RecBufOut];
1355 
1356  if (++Uart2RecBufOut >= UART_RECBUF_SIZE)
1357  {
1358  Uart2RecBufOut = 0;
1359  }
1360  Result = 1;
1361  }
1362 
1363  return (Result);
1364 }
1365 
1366 
1367 static void Uart2Flush(void)
1368 {
1369  Uart2Base[UART_FCR] = 0x07;
1370  Uart2RecBufIn = 0;
1371  Uart2RecBufOut = 0;
1372  Uart2RecMesIn = 0;
1373 }
1374 
1375 
1376 static UBYTE Uart2ReadData(UBYTE *pCmd,UBYTE *pData,UBYTE *pCheck,UBYTE *pFail)
1377 {
1378  UBYTE Byte;
1379  UBYTE Length;
1380  UBYTE Collect;
1381 
1382  Length = 0;
1383  *pFail = 0xFF;
1384  Collect = 1;
1385 
1386  while (Collect)
1387  {
1388 
1389  if (Uart2Read(&Byte))
1390  {
1391  if (Uart2RecMesIn == 0)
1392  { // Wait for data message start
1393 
1394  if (GET_MESSAGE_TYPE(Byte) == MESSAGE_DATA)
1395  {
1396 
1397  Uart2RecMesLng = GET_MESSAGE_LENGTH(Byte) + 2;
1398 
1399  if (Uart2RecMesLng <= UART_BUFFER_SIZE)
1400  { // Valid length
1401 
1402  Uart2RecMes[Uart2RecMesIn] = Byte;
1403  Uart2RecMesIn++;
1404  }
1405  }
1406  }
1407  else
1408  {
1409  Uart2RecMes[Uart2RecMesIn] = Byte;
1410 
1411  if (++Uart2RecMesIn >= Uart2RecMesLng)
1412  { // Message ready
1413 
1414  *pCmd = Uart2RecMes[0];
1415  *pFail ^= *pCmd;
1416 
1417  while (Length < (Uart2RecMesLng - 2))
1418  {
1419  pData[Length] = Uart2RecMes[Length + 1];
1420  *pFail ^= pData[Length];
1421  Length++;
1422  }
1423  *pCheck = Uart2RecMes[Length + 1];
1424  *pFail ^= *pCheck;
1425 
1426  Uart2RecMesIn = 0;
1427  Collect = 0;
1428  }
1429  }
1430  }
1431  else
1432  {
1433  Collect = 0;
1434  }
1435  }
1436 
1437  return (Length);
1438 }
1439 
1440 
1441 static UBYTE Uart2Write(UBYTE Byte)
1442 {
1443  UBYTE Result = 0;
1444 
1445  if (Uart2Base[UART_LSR] & 0x20)
1446  {
1447  Uart2Base[UART_THR] = Byte;
1448  Result = 1;
1449  }
1450 
1451  return (Result);
1452 }
1453 
1454 
1455 static void Uart2Setup(ULONG BitRate)
1456 {
1457  ULONG Divisor;
1458 
1459  Divisor = (ULONG)UART_CLOCK2 / (BitRate * (ULONG)16);
1460  Uart2Base[UART_LCR] = 0x03;
1461  Uart2Base[UART_MDR] = 0x00;
1462  Uart2Base[UART_DLL] = Divisor & 0xFF;
1463  Uart2Base[UART_DLH] = (Divisor >> 8) & 0xFF;
1464 
1465  Uart2Base[UART_FCR] = 0x01;
1466  Uart2Base[UART_MCR] = 0x00;
1467 
1468  Uart2Base[UART_IER] = 0x01;
1469 }
1470 
1471 
1472 static int Uart2Init(void)
1473 {
1474  int Result = -1;
1475 
1476  Uart2Base = NULL;
1477  IntSuccess[Uart2] = 0;
1478  if (UartBaseAddr[Uart2])
1479  {
1480  // Base address defined
1481 
1482  snprintf(Uart2Name,20,"%s.port%d",DEVICE1_NAME,Uart2 + 1);
1483 
1484  if (request_mem_region(UartBaseAddr[Uart2],0x38,MODULE_NAME) >= 0)
1485  {
1486  // Map base address
1487 
1488  Uart2Base = (ULONG*)ioremap(UartBaseAddr[Uart2],0x38);
1489  Base[Uart2] = Uart2Base;
1490  if (Uart2Base != NULL)
1491  {
1492  // Map success
1493 #ifdef DEBUG
1494  printk(" %s memory mapped from 0x%08lX\n",DEVICE1_NAME,(unsigned long)Uart2Base);
1495 #endif
1496  Result = 0;
1497 
1498  if (request_irq(UartIntr[Uart2],&Uart2Interrupt,IRQF_SHARED,Uart2Name,&Uart2Name) >= 0)
1499  {
1500 #ifdef DEBUG
1501  printk(" %s request interrupt success for UART2\n",DEVICE1_NAME);
1502 #endif
1503  IntSuccess[Uart2] = 1;
1504  }
1505  else
1506  {
1507  printk(" %s request interrupt failed for UART2\n",DEVICE1_NAME);
1508  Result = -EBUSY;
1509  }
1510 
1511  }
1512  }
1513  }
1514 
1515  return (Result);
1516 }
1517 
1518 
1519 void Uart2Exit(void)
1520 {
1521  Uart2Base[UART_IER] = 0x00;
1522  if (Uart2Base != NULL)
1523  {
1524  if (IntSuccess[Uart2])
1525  {
1526  free_irq(UartIntr[Uart2],Uart2Name);
1527  }
1528  iounmap(Uart2Base);
1529  }
1530 }
1531 
1532 #ifndef DISABLE_PRU_UARTS
1533 // UART 3 *********************************************************************
1534 
1535 static UBYTE Uart3RecMesLng;
1536 static UBYTE Uart3RecMes[UART_BUFFER_SIZE];
1537 static UBYTE Uart3RecMesIn;
1538 
1539 
1540 static UBYTE Uart3Read(UBYTE *pByte)
1541 {
1542  UBYTE Result = 0;
1543 
1544  if (lego_pru_read_bytes(1,pByte,1))
1545  {
1546  Result = 1;
1547  }
1548 
1549  return (Result);
1550 }
1551 
1552 
1553 static void Uart3Flush(void)
1554 {
1555  UBYTE Byte;
1556 
1557  while (Uart3Read(&Byte))
1558  {
1559  }
1560  Uart3RecMesIn = 0;
1561 }
1562 
1563 
1564 static UBYTE Uart3ReadData(UBYTE *pCmd,UBYTE *pData,UBYTE *pCheck,UBYTE *pFail)
1565 {
1566  UBYTE Byte;
1567  UBYTE Length;
1568  UBYTE Collect;
1569 
1570  Length = 0;
1571  *pFail = 0xFF;
1572  Collect = 1;
1573 
1574  while (Collect)
1575  {
1576 
1577  if (Uart3Read(&Byte))
1578  {
1579  if (Uart3RecMesIn == 0)
1580  { // Wait for data message start
1581 
1582  if (GET_MESSAGE_TYPE(Byte) == MESSAGE_DATA)
1583  {
1584 
1585  Uart3RecMesLng = GET_MESSAGE_LENGTH(Byte) + 2;
1586 
1587  if (Uart3RecMesLng <= UART_BUFFER_SIZE)
1588  { // Valid length
1589 
1590  Uart3RecMes[Uart3RecMesIn] = Byte;
1591  Uart3RecMesIn++;
1592  }
1593  }
1594  }
1595  else
1596  {
1597  Uart3RecMes[Uart3RecMesIn] = Byte;
1598 
1599  if (++Uart3RecMesIn >= Uart3RecMesLng)
1600  { // Message ready
1601 
1602  *pCmd = Uart3RecMes[0];
1603  *pFail ^= *pCmd;
1604 
1605  while (Length < (Uart3RecMesLng - 2))
1606  {
1607  pData[Length] = Uart3RecMes[Length + 1];
1608  *pFail ^= pData[Length];
1609  Length++;
1610  }
1611  *pCheck = Uart3RecMes[Length + 1];
1612  *pFail ^= *pCheck;
1613 
1614  Uart3RecMesIn = 0;
1615  Collect = 0;
1616  }
1617  }
1618  }
1619  else
1620  {
1621  Collect = 0;
1622  }
1623  }
1624 
1625  return (Length);
1626 }
1627 
1628 
1629 static UBYTE Uart3Write(UBYTE Byte)
1630 {
1631  UBYTE Result = 0;
1632 
1633  if (lego_pru_write_bytes(1,&Byte,1))
1634  {
1635  Result = 1;
1636  }
1637 
1638  return (Result);
1639 }
1640 
1641 
1642 static void Uart3Setup(ULONG BitRate)
1643 {
1644  lego_pru_set_baudrate(1,BitRate);
1645 }
1646 
1647 
1648 static void Uart3PortEnable(void)
1649 {
1650  lego_pru_uart_activate(1);
1651 }
1652 
1653 
1654 static void Uart3PortDisable(void)
1655 {
1656  lego_pru_uart_deactivate(1);
1657 }
1658 
1659 
1660 static int Uart3Init(void)
1661 {
1662  int Result = -1;
1663 
1664  Result = lego_pru_uart_init(1);
1665 
1666  return (Result);
1667 }
1668 
1669 
1670 void Uart3Exit(void)
1671 {
1672  lego_pru_uart_exit(1);
1673 }
1674 
1675 
1676 // UART 4 *********************************************************************
1677 
1678 static UBYTE Uart4RecMesLng;
1679 static UBYTE Uart4RecMes[UART_BUFFER_SIZE];
1680 static UBYTE Uart4RecMesIn;
1681 
1682 
1683 static UBYTE Uart4Read(UBYTE *pByte)
1684 {
1685  UBYTE Result = 0;
1686 
1687  if (lego_pru_read_bytes(0,pByte,1))
1688  {
1689  Result = 1;
1690  }
1691 
1692  return (Result);
1693 }
1694 
1695 
1696 static void Uart4Flush(void)
1697 {
1698  UBYTE Byte;
1699 
1700  while (Uart4Read(&Byte))
1701  {
1702  }
1703  Uart4RecMesIn = 0;
1704 }
1705 
1706 
1707 static UBYTE Uart4ReadData(UBYTE *pCmd,UBYTE *pData,UBYTE *pCheck,UBYTE *pFail)
1708 {
1709  UBYTE Byte;
1710  UBYTE Length;
1711  UBYTE Collect;
1712 
1713  Length = 0;
1714  *pFail = 0xFF;
1715  Collect = 1;
1716 
1717  while (Collect)
1718  {
1719 
1720  if (Uart4Read(&Byte))
1721  {
1722  if (Uart4RecMesIn == 0)
1723  { // Wait for data message start
1724 
1725  if (GET_MESSAGE_TYPE(Byte) == MESSAGE_DATA)
1726  {
1727 
1728  Uart4RecMesLng = GET_MESSAGE_LENGTH(Byte) + 2;
1729 
1730  if (Uart4RecMesLng <= UART_BUFFER_SIZE)
1731  { // Valid length
1732 
1733  Uart4RecMes[Uart4RecMesIn] = Byte;
1734  Uart4RecMesIn++;
1735  }
1736  }
1737  }
1738  else
1739  {
1740  Uart4RecMes[Uart4RecMesIn] = Byte;
1741 
1742  if (++Uart4RecMesIn >= Uart4RecMesLng)
1743  { // Message ready
1744 
1745  *pCmd = Uart4RecMes[0];
1746  *pFail ^= *pCmd;
1747 
1748  while (Length < (Uart4RecMesLng - 2))
1749  {
1750  pData[Length] = Uart4RecMes[Length + 1];
1751  *pFail ^= pData[Length];
1752  Length++;
1753  }
1754  *pCheck = Uart4RecMes[Length + 1];
1755  *pFail ^= *pCheck;
1756 
1757  Uart4RecMesIn = 0;
1758  Collect = 0;
1759  }
1760  }
1761  }
1762  else
1763  {
1764  Collect = 0;
1765  }
1766  }
1767 
1768  return (Length);
1769 }
1770 
1771 
1772 static UBYTE Uart4Write(UBYTE Byte)
1773 {
1774  UBYTE Result = 0;
1775 
1776  if (lego_pru_write_bytes(0,&Byte,1))
1777  {
1778  Result = 1;
1779  }
1780 
1781  return (Result);
1782 }
1783 
1784 
1785 static void Uart4Setup(ULONG BitRate)
1786 {
1787  lego_pru_set_baudrate(0,BitRate);
1788 }
1789 
1790 
1791 static void Uart4PortEnable(void)
1792 {
1793  lego_pru_uart_activate(0);
1794 }
1795 
1796 
1797 static void Uart4PortDisable(void)
1798 {
1799  lego_pru_uart_deactivate(0);
1800 }
1801 
1802 
1803 static int Uart4Init(void)
1804 {
1805  int Result = -1;
1806 
1807  Result = lego_pru_uart_init(0);
1808 
1809  return (Result);
1810 }
1811 
1812 
1813 void Uart4Exit(void)
1814 {
1815  lego_pru_uart_exit(0);
1816 }
1817 
1818 #endif
1819 
1820 
1821 // DEVICE1 ********************************************************************
1822 
1823 
1824 #define INFODATA_INIT 0x00000000L
1825 #define INFODATA_CMD_TYPE 0x00000001L
1826 #define INFODATA_CMD_MODES 0x00000002L
1827 #define INFODATA_CMD_SPEED 0x00000004L
1828 
1829 #define INFODATA_INFO_NAME 0x00000100L
1830 #define INFODATA_INFO_RAW 0x00000200L
1831 #define INFODATA_INFO_PCT 0x00000400L
1832 #define INFODATA_INFO_SI 0x00000800L
1833 #define INFODATA_INFO_SYMBOL 0x00001000L
1834 #define INFODATA_INFO_FORMAT 0x00002000L
1835 
1836 #define INFODATA_CLEAR (~(INFODATA_INFO_NAME | INFODATA_INFO_RAW | INFODATA_INFO_PCT | INFODATA_INFO_SI | INFODATA_INFO_SYMBOL | INFODATA_INFO_FORMAT))
1837 
1838 #define INFODATA_NEEDED (INFODATA_CMD_TYPE | INFODATA_CMD_MODES | INFODATA_INFO_NAME | INFODATA_INFO_FORMAT)
1839 
1840 
1841 enum UART_STATE
1842 {
1843  UART_IDLE,
1844  UART_INIT,
1845  UART_RESTART,
1846  UART_ENABLE,
1847  UART_FLUSH,
1848  UART_SYNC,
1849  UART_MESSAGE_START,
1850  UART_CMD,
1851  UART_INFO,
1852  UART_DATA,
1853  UART_DATA_COPY,
1854  UART_ACK_WAIT,
1855  UART_ACK_INFO,
1856  UART_CMD_ERROR,
1857  UART_INFO_ERROR,
1858  UART_TERMINAL,
1859  UART_DATA_ERROR,
1860  UART_ERROR,
1861  UART_EXIT,
1862  UART_STATES
1863 };
1864 
1865 
1866 char UartStateText[UART_STATES][50] =
1867 {
1868  "IDLE\n",
1869  "INIT",
1870  "UART_RESTART",
1871  "ENABLE",
1872  "FLUSH",
1873  "SYNC",
1874  "MESSAGE_START",
1875  "CMD",
1876  "INFO",
1877  "DATA",
1878  "DATA_COPY",
1879  "ACK_WAIT",
1880  "ACK_INFO",
1881  "CMD_ERROR",
1882  "INFO_ERROR",
1883  "TERMINAL",
1884  "DATA_ERROR",
1885  "ERROR",
1886  "EXIT"
1887 };
1888 
1889 
1890 typedef struct
1891 {
1892  ULONG InfoData;
1893  ULONG BitRate;
1894  ULONG BitRateMax;
1895  UWORD Timer;
1896  UWORD WatchDog;
1897  UWORD BreakTimer;
1898  UBYTE Initialised;
1899  UBYTE ChangeMode;
1900  UBYTE State;
1901  UBYTE OldState;
1902  UBYTE SubState;
1903  UBYTE Cmd;
1904  UBYTE InfoCmd;
1905  UBYTE Check;
1906  UBYTE Types;
1907  UBYTE Views;
1908  UBYTE Mode;
1909  UBYTE Type;
1910  UBYTE DataOk;
1911  UBYTE DataErrors;
1912  SBYTE Name[TYPE_NAME_LENGTH + 1];
1913  UBYTE InLength;
1914  UBYTE InPointer;
1915  UBYTE OutLength;
1916  UBYTE OutPointer;
1917  UBYTE InBuffer[UART_BUFFER_SIZE];
1918  UBYTE OutBuffer[UART_BUFFER_SIZE];
1919 }
1920 UARTPORT;
1921 
1922 
1923 UARTPORT UartPortDefault =
1924 {
1925  INFODATA_INIT, // InfoData
1926  (ULONG)LOWEST_BITRATE, // BitRate
1927  (ULONG)LOWEST_BITRATE, // BitRateMax
1928  0, // Timer
1929  0, // WatchDog
1930  0, // BreakTimer
1931  0, // Initialised
1932  0, // ChangeMode
1933  UART_IDLE, // State
1934  -1, // OldState
1935  0, // SubState
1936  0, // Cmd
1937  0, // InfoCmd
1938  0, // Check
1939  0, // Types
1940  0, // Views
1941  0, // Mode
1942  TYPE_UNKNOWN, // Type
1943  0, // DataOk
1944  0, // DataErrors
1945  "", // Name
1946  0, // InLength
1947  0, // InPointer
1948  0, // OutLength
1949  0, // OutPointer
1950 };
1951 
1952 TYPES TypeData[INPUTS][MAX_DEVICE_MODES];
1953 DATA8 Changed[INPUTS][MAX_DEVICE_MODES];
1954 
1955 
1956 #define UART_TIMER_RESOLUTION 10 // [100uS]
1957 
1958 #define UART_BREAK_TIME 1000 // [100uS]
1959 #define UART_TERMINAL_DELAY 20000 // [100uS]
1960 #define UART_CHANGE_BITRATE_DELAY 100 // [100uS]
1961 #define UART_ACK_DELAY 100 // [100uS]
1962 #define UART_SHOW_TIME 2500 // [100uS]
1963 
1964 #define UART_WATCHDOG_TIME 1000 // [100uS]
1965 
1966 #define UART_ALLOWABLE_DATA_ERRORS 6
1967 
1968 UBYTE UartConfigured[INPUTS];
1969 UARTPORT UartPort[INPUTS];
1970 
1971 static UART UartDefault;
1972 static UART *pUart = &UartDefault;
1973 
1974 static struct hrtimer Device1Timer;
1975 static ktime_t Device1Time;
1976 
1977 static UBYTE TestMode = 0;
1978 
1979 static void UartPortDisable(UBYTE Port)
1980 {
1981  switch (Port)
1982  {
1983  case Uart1 :
1984  {
1985  }
1986  break;
1987 
1988  case Uart2 :
1989  {
1990  }
1991  break;
1992 
1993 #ifndef DISABLE_PRU_UARTS
1994  case Uart3 :
1995  {
1996  Uart3PortDisable();
1997  }
1998  break;
1999 
2000  case Uart4 :
2001  {
2002  Uart4PortDisable();
2003  }
2004  break;
2005 #endif
2006 
2007  }
2008  PUARTHigh(Port,INPUT_UART_BUFFER);
2009 }
2010 
2011 
2012 static void UartPortFlush(UBYTE Port)
2013 {
2014  switch (Port)
2015  {
2016  case Uart1 :
2017  {
2018  Uart1Flush();
2019  }
2020  break;
2021 
2022  case Uart2 :
2023  {
2024  Uart2Flush();
2025  }
2026  break;
2027 
2028 #ifndef DISABLE_PRU_UARTS
2029  case Uart3 :
2030  {
2031  Uart3Flush();
2032  }
2033  break;
2034 
2035  case Uart4 :
2036  {
2037  Uart4Flush();
2038  }
2039  break;
2040 #endif
2041 
2042  }
2043 }
2044 
2045 
2046 static void UartPortEnable(UBYTE Port)
2047 {
2048  SetGpio(InputUartPin[Port][INPUT_UART_TXD].Pin);
2049  PUARTLow(Port,INPUT_UART_BUFFER);
2050 
2051  switch (Port)
2052  {
2053  case Uart1 :
2054  {
2055  Uart1Flush();
2056  }
2057  break;
2058 
2059  case Uart2 :
2060  {
2061  Uart2Flush();
2062  }
2063  break;
2064 
2065 #ifndef DISABLE_PRU_UARTS
2066  case Uart3 :
2067  {
2068  Uart3PortEnable();
2069  }
2070  break;
2071 
2072  case Uart4 :
2073  {
2074  Uart4PortEnable();
2075  }
2076  break;
2077 #endif
2078 
2079  }
2080 }
2081 
2082 
2083 static UBYTE UartPortSend(UBYTE Port,UBYTE Byte)
2084 {
2085  UBYTE Result = 1;
2086 
2087  switch (Port)
2088  {
2089  case Uart1 :
2090  {
2091  Result = Uart1Write(Byte);
2092  }
2093  break;
2094 
2095  case Uart2 :
2096  {
2097  Result = Uart2Write(Byte);
2098  }
2099  break;
2100 
2101 #ifndef DISABLE_PRU_UARTS
2102  case Uart3 :
2103  {
2104  Result = Uart3Write(Byte);
2105  }
2106  break;
2107 
2108  case Uart4 :
2109  {
2110  Result = Uart4Write(Byte);
2111  }
2112  break;
2113 #endif
2114 
2115  }
2116 
2117  return (Result);
2118 }
2119 
2120 
2121 static UBYTE UartPortReceive(UBYTE Port,UBYTE *pByte)
2122 {
2123  UBYTE Result = 0;
2124 
2125  switch (Port)
2126  {
2127  case Uart1 :
2128  {
2129  Result = Uart1Read(pByte);
2130  }
2131  break;
2132 
2133  case Uart2 :
2134  {
2135  Result = Uart2Read(pByte);
2136  }
2137  break;
2138 
2139 #ifndef DISABLE_PRU_UARTS
2140  case Uart3 :
2141  {
2142  Result = Uart3Read(pByte);
2143  }
2144  break;
2145 
2146  case Uart4 :
2147  {
2148  Result = Uart4Read(pByte);
2149  }
2150  break;
2151 #endif
2152 
2153  }
2154 #ifdef HIGHDEBUG
2155  if (Result)
2156  {
2157  snprintf(UartBuffer,UARTBUFFERSIZE,">%d 0x%02X\r\n",Port,*pByte);
2158  UartWrite(UartBuffer);
2159  }
2160 #endif
2161 
2162  return (Result);
2163 }
2164 
2165 
2166 static UBYTE UartPortReadData(UBYTE Port,UBYTE *pCmd,UBYTE *pData,UBYTE *pCheck,UBYTE *pFail)
2167 {
2168  UBYTE Result = 0;
2169 
2170  switch (Port)
2171  {
2172  case Uart1 :
2173  {
2174  Result = Uart1ReadData(pCmd,pData,pCheck,pFail);
2175  }
2176  break;
2177 
2178  case Uart2 :
2179  {
2180  Result = Uart2ReadData(pCmd,pData,pCheck,pFail);
2181  }
2182  break;
2183 
2184 #ifndef DISABLE_PRU_UARTS
2185  case Uart3 :
2186  {
2187  Result = Uart3ReadData(pCmd,pData,pCheck,pFail);
2188  }
2189  break;
2190 
2191  case Uart4 :
2192  {
2193  Result = Uart4ReadData(pCmd,pData,pCheck,pFail);
2194  }
2195  break;
2196 #endif
2197 
2198  }
2199 
2200  return (Result);
2201 }
2202 
2203 
2204 static void UartPortSetup(UBYTE Port,ULONG BitRate)
2205 {
2206 #ifdef HIGHDEBUG
2207  snprintf(UartBuffer,UARTBUFFERSIZE," %d SETTING BITRATE = %lu\r\n",Port,(unsigned long)BitRate);
2208  UartWrite(UartBuffer);
2209 #endif
2210 
2211  switch (Port)
2212  {
2213  case Uart1 :
2214  {
2215  Uart1Setup(BitRate);
2216  }
2217  break;
2218 
2219  case Uart2 :
2220  {
2221  Uart2Setup(BitRate);
2222  }
2223  break;
2224 
2225 #ifndef DISABLE_PRU_UARTS
2226  case Uart3 :
2227  {
2228  Uart3Setup(BitRate);
2229  }
2230  break;
2231 
2232  case Uart4 :
2233  {
2234  Uart4Setup(BitRate);
2235  }
2236  break;
2237 #endif
2238 
2239  }
2240 }
2241 
2242 
2243 UBYTE WriteRequest[INPUTS];
2244 
2245 
2246 static enum hrtimer_restart Device1TimerInterrupt1(struct hrtimer *pTimer)
2247 {
2248  UBYTE Port;
2249  UBYTE Byte;
2250  UBYTE CrcError = 0;
2251  UBYTE Tmp = 0;
2252  ULONG TmpL;
2253  UBYTE Chksum;
2254  UBYTE Pointer;
2255  UBYTE Mode;
2256  UBYTE TmpBuffer[UART_DATA_LENGTH];
2257 #ifdef DEBUG_TRACE_US
2258  UWORD In;
2259 #endif
2260 #ifdef DEBUG_TRACE_ANGLE
2261  UWORD Angle;
2262 #endif
2263 
2264  hrtimer_forward_now(pTimer,Device1Time);
2265 
2266  for (Port = 0;Port < NO_OF_INPUT_PORTS;Port++)
2267  { // look at one port at a time
2268 
2269  if ((UartPort[Port].State > UART_ENABLE) && (!TestMode))
2270  { // If port active
2271 
2272  if (++UartPort[Port].BreakTimer >= (UART_BREAK_TIME / UART_TIMER_RESOLUTION))
2273  { // Reset state machine if break received
2274 
2275  if (PUARTRead(Port,INPUT_UART_PIN6))
2276  {
2277 
2278 #ifdef DEBUG_D_UART_ERROR
2279  snprintf(UartBuffer,UARTBUFFERSIZE," %d BREAK\r\n",Port);
2280  UartWrite(UartBuffer);
2281 #endif
2282 
2283  UartPortDisable(Port);
2284  UartPort[Port] = UartPortDefault;
2285  UartPortEnable(Port);
2286  UartPortSetup(Port,UartPort[Port].BitRate);
2287  for (Tmp = 0;Tmp < MAX_DEVICE_MODES;Tmp++)
2288  {
2289  TypeData[Port][Tmp] = TypeDefaultUart[0];
2290  Changed[Port][Tmp] = 0;
2291  }
2292 #ifndef DISABLE_FAST_DATALOG_BUFFER
2293  (*pUart).Actual[Port] = 0;
2294  (*pUart).LogIn[Port] = 0;
2295 #endif
2296  (*pUart).Status[Port] = 0;
2297  UartPortFlush(Port);
2298  UartPort[Port].State = UART_SYNC;
2299  }
2300  }
2301  if (PUARTRead(Port,INPUT_UART_PIN6))
2302  {
2303  UartPort[Port].BreakTimer = 0;
2304  }
2305  }
2306 
2307  if (Port != DEBUG_UART)
2308  { // If port not used for debug
2309 
2310  #ifdef DEBUG
2311  ShowTimer[Port]++;
2312  #endif
2313 
2314  if (!TestMode)
2315  {
2316 
2317  switch (UartPort[Port].State)
2318  { // Main state machine
2319 
2320  case UART_IDLE :
2321  { // Port inactive
2322 
2323  (*pUart).Status[Port] &= ~UART_WRITE_REQUEST;
2324  (*pUart).Status[Port] &= ~UART_DATA_READY;
2325  WriteRequest[Port] = 0;
2326  }
2327  break;
2328 
2329  case UART_INIT :
2330  { // Initialise port hardware
2331 
2332  PUARTFloat(Port,INPUT_UART_PIN5);
2333  PUARTFloat(Port,INPUT_UART_PIN6);
2334  UartPort[Port].State = UART_ENABLE;
2335  }
2336  break;
2337 
2338  case UART_RESTART :
2339  {
2340  UartPortDisable(Port);
2341  UartPort[Port].State = UART_ENABLE;
2342  }
2343  break;
2344 
2345  case UART_ENABLE :
2346  { // Initialise port variables
2347 
2348  UartPort[Port] = UartPortDefault;
2349  UartPortEnable(Port);
2350  UartPortSetup(Port,UartPort[Port].BitRate);
2351  for (Tmp = 0;Tmp < MAX_DEVICE_MODES;Tmp++)
2352  {
2353  TypeData[Port][Tmp] = TypeDefaultUart[0];
2354  Changed[Port][Tmp] = 0;
2355  }
2356  #ifndef DISABLE_FAST_DATALOG_BUFFER
2357  (*pUart).Actual[Port] = 0;
2358  (*pUart).LogIn[Port] = 0;
2359  #endif
2360  (*pUart).Status[Port] = 0;
2361  UartPortFlush(Port);
2362  UartPort[Port].State = UART_SYNC;
2363  }
2364  break;
2365 
2366  case UART_SYNC :
2367  { // Look for UART_CMD, TYPE in rolling buffer window
2368 
2369  if (UartPortReceive(Port,&Byte))
2370  {
2371  if (UartPort[Port].InPointer < 3)
2372  { // 0,1,2
2373  UartPort[Port].InBuffer[UartPort[Port].InPointer] = Byte;
2374  UartPort[Port].InPointer++;
2375  }
2376  if (UartPort[Port].InPointer >= 3)
2377  {
2378  // Validate
2379  UartPort[Port].Check = 0xFF;
2380  for (Tmp = 0;Tmp < 2;Tmp++)
2381  {
2382  UartPort[Port].Check ^= UartPort[Port].InBuffer[Tmp];
2383  }
2384  if ((UartPort[Port].Check == UartPort[Port].InBuffer[2]) && (UartPort[Port].InBuffer[0] == 0x40) && (UartPort[Port].InBuffer[1] > 0) && (UartPort[Port].InBuffer[1] <= MAX_VALID_TYPE))
2385  {
2386  UartPort[Port].Type = UartPort[Port].InBuffer[1];
2387  UartPort[Port].InfoData |= INFODATA_CMD_TYPE;
2388  #ifdef HIGHDEBUG
2389  snprintf(UartBuffer,UARTBUFFERSIZE," %d TYPE = %-3u\r\n",Port,(UWORD)UartPort[Port].Type & 0xFF);
2390  UartWrite(UartBuffer);
2391  #endif
2392  UartPort[Port].State = UART_MESSAGE_START;
2393  }
2394  else
2395  {
2396  #ifdef DEBUG_D_UART_ERROR
2397  // snprintf(UartBuffer,UARTBUFFERSIZE,"[%02X]",Byte);
2398  // UartWrite(UartBuffer);
2399  // snprintf(UartBuffer,UARTBUFFERSIZE," %d No sync %02X %02X %02X\r\n",Port,UartPort[Port].InBuffer[0],UartPort[Port].InBuffer[1],UartPort[Port].InBuffer[2]);
2400  // UartWrite(UartBuffer);
2401  #endif
2402  for (Tmp = 0;Tmp < 2;Tmp++)
2403  {
2404  UartPort[Port].InBuffer[Tmp] = UartPort[Port].InBuffer[Tmp + 1];
2405  }
2406 
2407  UartPort[Port].InPointer--;
2408  }
2409  }
2410  }
2411  if ((++(UartPort[Port].Timer) >= (UART_TERMINAL_DELAY / UART_TIMER_RESOLUTION)))
2412  {
2413  UartPort[Port].BitRate = 115200;
2414  UartPortSetup(Port,UartPort[Port].BitRate);
2415  TypeData[Port][0] = TypeDefaultUart[1];
2416  UartPort[Port].State = UART_TERMINAL;
2417  Changed[Port][0] = 1;
2418  (*pUart).Status[Port] |= UART_PORT_CHANGED;
2419  }
2420  }
2421  break;
2422 
2423  default :
2424  { // Get sensor informations
2425 
2426  if (UartPortReceive(Port,&Byte))
2427  {
2428 
2429  switch (UartPort[Port].State)
2430  {
2431 
2432  //** INTERPRETER **************************************************************
2433 
2434  case UART_MESSAGE_START :
2435  {
2436  UartPort[Port].InPointer = 0;
2437  UartPort[Port].SubState = 0;
2438  UartPort[Port].Check = 0xFF;
2439  UartPort[Port].Cmd = Byte;
2440 
2441  switch (GET_MESSAGE_TYPE(Byte))
2442  {
2443  case MESSAGE_CMD :
2444  {
2445  UartPort[Port].InLength = GET_MESSAGE_LENGTH(Byte);
2446  UartPort[Port].State = UART_CMD;
2447  }
2448  break;
2449 
2450  case MESSAGE_INFO :
2451  {
2452  UartPort[Port].InLength = GET_MESSAGE_LENGTH(Byte);
2453  UartPort[Port].State = UART_INFO;
2454  }
2455  break;
2456 
2457  case MESSAGE_DATA :
2458  {
2459  }
2460  break;
2461 
2462  default :
2463  {
2464  switch (Byte)
2465  {
2466  case BYTE_ACK :
2467  {
2468  #ifdef HIGHDEBUG
2469  snprintf(UartBuffer,UARTBUFFERSIZE," %d ACK RECEIVED\r\n",Port);
2470  UartWrite(UartBuffer);
2471  #endif
2472  if (UartPort[Port].Types == 0)
2473  {
2474  if ((UartPort[Port].InfoData & INFODATA_NEEDED) == INFODATA_NEEDED)
2475  {
2476  UartPort[Port].Timer = 0;
2477  UartPort[Port].State = UART_ACK_WAIT;
2478  }
2479  else
2480  {
2481  UartPort[Port].State = UART_INFO_ERROR;
2482  }
2483  }
2484  else
2485  {
2486  UartPort[Port].State = UART_INFO_ERROR;
2487  }
2488  }
2489  break;
2490 
2491  case BYTE_NACK :
2492  {
2493  }
2494  break;
2495 
2496  case BYTE_SYNC :
2497  {
2498  }
2499  break;
2500 
2501  default :
2502  {
2503  }
2504  break;
2505 
2506  }
2507 
2508  }
2509  break;
2510 
2511  }
2512  }
2513  break;
2514 
2515  //** CMD **********************************************************************
2516 
2517  case UART_CMD :
2518  { // Command message in progress
2519 
2520  if (UartPort[Port].InPointer < UartPort[Port].InLength)
2521  {
2522  UartPort[Port].InBuffer[UartPort[Port].InPointer] = Byte;
2523  UartPort[Port].InPointer++;
2524  }
2525  else
2526  { // Message complete
2527 
2528  UartPort[Port].InBuffer[UartPort[Port].InPointer] = 0;
2529  UartPort[Port].State = UART_MESSAGE_START;
2530 
2531  if (UartPort[Port].Check != Byte)
2532  { // Check not correct
2533  #ifdef DEBUG_D_UART_ERROR
2534  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
2535  UartWrite(UartBuffer);
2536  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
2537  {
2538  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].InBuffer[Tmp] & 0xFF);
2539  UartWrite(UartBuffer);
2540  }
2541  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
2542  UartWrite(UartBuffer);
2543  #endif
2544  UartPort[Port].State = UART_CMD_ERROR;
2545  }
2546  else
2547  { // Command message valid
2548  #ifdef HIGHDEBUG
2549  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
2550  UartWrite(UartBuffer);
2551  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
2552  {
2553  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].InBuffer[Tmp] & 0xFF);
2554  UartWrite(UartBuffer);
2555  }
2556  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
2557  UartWrite(UartBuffer);
2558  #endif
2559  switch (GET_CMD_COMMAND(UartPort[Port].Cmd))
2560  { // Command message type
2561 
2562  case CMD_MODES :
2563  { // Number of modes
2564 
2565  if ((UartPort[Port].InBuffer[0] >= 0) && (UartPort[Port].InBuffer[0] < MAX_DEVICE_MODES))
2566  { // Number of modes valid
2567 
2568  if ((UartPort[Port].InfoData & INFODATA_CMD_MODES))
2569  { // Modes already given
2570 
2571  #ifdef DEBUG_D_UART_ERROR
2572  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d MODES ALREADY GIVEN\r\n",Port);
2573  UartWrite(UartBuffer);
2574  #endif
2575  UartPort[Port].State = UART_CMD_ERROR;
2576  }
2577  else
2578  {
2579 
2580  UartPort[Port].Types = UartPort[Port].InBuffer[0] + 1;
2581  if (UartPort[Port].InLength >= 2)
2582  { // Both modes and views present
2583 
2584  UartPort[Port].Views = UartPort[Port].InBuffer[1] + 1;
2585  #ifdef HIGHDEBUG
2586  snprintf(UartBuffer,UARTBUFFERSIZE," %d MODES = %u VIEWS = %u\r\n",Port,(UWORD)UartPort[Port].Types & 0xFF,(UWORD)UartPort[Port].Views & 0xFF);
2587  UartWrite(UartBuffer);
2588  #endif
2589  }
2590  else
2591  { // Only modes present
2592 
2593  UartPort[Port].Views = UartPort[Port].Types;
2594  #ifdef HIGHDEBUG
2595  snprintf(UartBuffer,UARTBUFFERSIZE," %d MODES = %u = VIEWS\r\n",Port,(UWORD)UartPort[Port].Types & 0xFF);
2596  UartWrite(UartBuffer);
2597  #endif
2598  }
2599  UartPort[Port].InfoData |= INFODATA_CMD_MODES;
2600  }
2601  }
2602  else
2603  { // Number of modes invalid
2604  #ifdef DEBUG_D_UART_ERROR
2605  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d MODES ERROR %u\r\n",Port,(UWORD)UartPort[Port].Types & 0xFF);
2606  UartWrite(UartBuffer);
2607  #endif
2608  UartPort[Port].State = UART_CMD_ERROR;
2609  }
2610  }
2611  break;
2612 
2613  case CMD_SPEED :
2614  { // Highest communication speed
2615 
2616  TmpL = 0;
2617  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
2618  {
2619  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp] << (8 * Tmp);
2620  }
2621 
2622  if ((TmpL >= LOWEST_BITRATE) && (TmpL <= HIGHEST_BITRATE))
2623  { // Speed valid
2624 
2625  if ((UartPort[Port].InfoData & INFODATA_CMD_SPEED))
2626  { // Speed already given
2627 
2628  #ifdef DEBUG_D_UART_ERROR
2629  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d SPEED ALREADY GIVEN\r\n",Port);
2630  UartWrite(UartBuffer);
2631  #endif
2632  UartPort[Port].State = UART_CMD_ERROR;
2633  }
2634  else
2635  {
2636  if ((UartPort[Port].BitRate != LOWEST_BITRATE) && (TmpL <= MIDLE_BITRATE))
2637  { // allow bit rate adjust
2638  #ifdef HIGHDEBUG
2639  snprintf(UartBuffer,UARTBUFFERSIZE," %d SPEED ADJUST\r\n",Port);
2640  UartWrite(UartBuffer);
2641  #endif
2642  UartPort[Port].BitRateMax = (UartPort[Port].BitRate * TmpL) / LOWEST_BITRATE;
2643  }
2644  else
2645  {
2646 
2647  UartPort[Port].BitRateMax = TmpL;
2648  }
2649  #ifdef HIGHDEBUG
2650  snprintf(UartBuffer,UARTBUFFERSIZE," %d SPEED = %lu\r\n",Port,(unsigned long)UartPort[Port].BitRateMax);
2651  UartWrite(UartBuffer);
2652  #endif
2653  UartPort[Port].InfoData |= INFODATA_CMD_SPEED;
2654  }
2655  }
2656  else
2657  { // Speed invalid
2658  #ifdef DEBUG_D_UART_ERROR
2659  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d SPEED ERROR\r\n",Port);
2660  UartWrite(UartBuffer);
2661  #endif
2662  UartPort[Port].State = UART_CMD_ERROR;
2663  }
2664  }
2665  break;
2666 
2667  }
2668  }
2669  }
2670  }
2671  break;
2672 
2673  //** INFO *********************************************************************
2674 
2675  case UART_INFO :
2676  { // Info messages in progress
2677 
2678  switch (UartPort[Port].SubState)
2679  {
2680  case 0 :
2681  {
2682  UartPort[Port].InfoCmd = Byte;
2683 
2684  // validate length
2685 
2686  switch (GET_INFO_COMMAND(UartPort[Port].InfoCmd))
2687  {
2688 
2689  case INFO_FORMAT :
2690  {
2691  if (UartPort[Port].InLength < 2)
2692  {
2693  #ifdef DEBUG_D_UART_ERROR
2694  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d FORMAT ERROR\r\n",Port);
2695  UartWrite(UartBuffer);
2696  #endif
2697  UartPort[Port].State = UART_INFO_ERROR;
2698  }
2699  }
2700  break;
2701 
2702  }
2703  UartPort[Port].SubState++;
2704  }
2705  break;
2706 
2707  default :
2708  {
2709  if (UartPort[Port].InPointer < UartPort[Port].InLength)
2710  { // Info message in progress
2711 
2712  UartPort[Port].InBuffer[UartPort[Port].InPointer] = Byte;
2713  UartPort[Port].InPointer++;
2714  }
2715  else
2716  { // Message complete
2717 
2718  UartPort[Port].InBuffer[UartPort[Port].InPointer] = 0;
2719  UartPort[Port].State = UART_MESSAGE_START;
2720 
2721  if (UartPort[Port].Check != Byte)
2722  {
2723  #ifdef DEBUG_D_UART_ERROR
2724  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X ",Port,UartPort[Port].Cmd & 0xFF);
2725  UartWrite(UartBuffer);
2726  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X[",UartPort[Port].InfoCmd & 0xFF);
2727  UartWrite(UartBuffer);
2728  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
2729  {
2730  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].InBuffer[Tmp] & 0xFF);
2731  UartWrite(UartBuffer);
2732  }
2733  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
2734  UartWrite(UartBuffer);
2735  #endif
2736  UartPort[Port].State = UART_INFO_ERROR;
2737  }
2738  else
2739  {
2740  #ifdef HIGHDEBUG
2741  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X ",Port,UartPort[Port].Cmd & 0xFF);
2742  UartWrite(UartBuffer);
2743  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X[",UartPort[Port].InfoCmd & 0xFF);
2744  UartWrite(UartBuffer);
2745  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
2746  {
2747  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].InBuffer[Tmp] & 0xFF);
2748  UartWrite(UartBuffer);
2749  }
2750  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
2751  UartWrite(UartBuffer);
2752  #endif
2753 
2754  Mode = GET_MODE(UartPort[Port].Cmd);
2755 
2756  switch (GET_INFO_COMMAND(UartPort[Port].InfoCmd))
2757  { // Info mesage type
2758 
2759  case INFO_NAME :
2760  { // Device name
2761 
2762  UartPort[Port].InfoData &= INFODATA_CLEAR;
2763  if ((UartPort[Port].InBuffer[0] >= 'A') && (UartPort[Port].InBuffer[0] <= 'z') && (strlen(UartPort[Port].InBuffer) <= TYPE_NAME_LENGTH))
2764  {
2765  snprintf((char*)UartPort[Port].Name,TYPE_NAME_LENGTH + 1,"%s",(char*)UartPort[Port].InBuffer);
2766  #ifdef HIGHDEBUG
2767  snprintf(UartBuffer,UARTBUFFERSIZE," %d NAME = %s\r\n",Port,UartPort[Port].Name);
2768  UartWrite(UartBuffer);
2769  #endif
2770  TypeData[Port][Mode].Mode = Mode;
2771  UartPort[Port].InfoData |= INFODATA_INFO_NAME;
2772  }
2773  else
2774  {
2775  #ifdef DEBUG_D_UART_ERROR
2776  UartPort[Port].InBuffer[TYPE_NAME_LENGTH] = 0;
2777  snprintf(UartBuffer,UARTBUFFERSIZE," f %d NAME = %s\r\n",Port,UartPort[Port].InBuffer);
2778  UartWrite(UartBuffer);
2779  #endif
2780  UartPort[Port].State = UART_INFO_ERROR;
2781  }
2782  }
2783  break;
2784 
2785  case INFO_RAW :
2786  { // Raw scaling values
2787 
2788  TmpL = 0;
2789  for (Tmp = 0;(Tmp < UartPort[Port].InLength) && (Tmp < 4);Tmp++)
2790  {
2791  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp] << (8 * Tmp);
2792  }
2793  *((ULONG*)&TypeData[Port][Mode].RawMin) = TmpL;
2794  TmpL = 0;
2795  for (Tmp = 0;(Tmp < (UartPort[Port].InLength - 4)) && (Tmp < 4);Tmp++)
2796  {
2797  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp + 4] << (8 * Tmp);
2798  }
2799  *((ULONG*)&TypeData[Port][Mode].RawMax) = TmpL;
2800 
2801  if (TypeData[Port][Mode].Mode == GET_MODE(UartPort[Port].Cmd))
2802  {
2803  if ((UartPort[Port].InfoData & INFODATA_INFO_RAW))
2804  { // Raw already given
2805 
2806  #ifdef DEBUG_D_UART_ERROR
2807  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d RAW ALREADY GIVEN\r\n",Port);
2808  UartWrite(UartBuffer);
2809  #endif
2810  UartPort[Port].State = UART_INFO_ERROR;
2811  }
2812  else
2813  {
2814  #ifdef HIGHDEBUG
2815  snprintf(UartBuffer,UARTBUFFERSIZE," %d RAW = Min..Max\r\n",Port);
2816  UartWrite(UartBuffer);
2817  #endif
2818  UartPort[Port].InfoData |= INFODATA_INFO_RAW;
2819  }
2820  }
2821  else
2822  {
2823  #ifdef DEBUG_D_UART_ERROR
2824  snprintf(UartBuffer,UARTBUFFERSIZE," f %d RAW = Min..Max\r\n",Port);
2825  UartWrite(UartBuffer);
2826  #endif
2827  UartPort[Port].State = UART_INFO_ERROR;
2828  }
2829  }
2830  break;
2831 
2832  case INFO_PCT :
2833  { // Pct scaling values
2834 
2835  TmpL = 0;
2836  for (Tmp = 0;(Tmp < UartPort[Port].InLength) && (Tmp < 4);Tmp++)
2837  {
2838  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp] << (8 * Tmp);
2839  }
2840  *((ULONG*)&TypeData[Port][Mode].PctMin) = TmpL;
2841  TmpL = 0;
2842  for (Tmp = 0;(Tmp < (UartPort[Port].InLength - 4)) && (Tmp < 4);Tmp++)
2843  {
2844  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp + 4] << (8 * Tmp);
2845  }
2846  *((ULONG*)&TypeData[Port][Mode].PctMax) = TmpL;
2847 
2848  if (TypeData[Port][Mode].Mode == GET_MODE(UartPort[Port].Cmd))
2849  { // Mode valid
2850 
2851  if ((UartPort[Port].InfoData & INFODATA_INFO_PCT))
2852  { // Pct already given
2853 
2854  #ifdef DEBUG_D_UART_ERROR
2855  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d PCT ALREADY GIVEN\r\n",Port);
2856  UartWrite(UartBuffer);
2857  #endif
2858  UartPort[Port].State = UART_INFO_ERROR;
2859  }
2860  else
2861  {
2862  #ifdef HIGHDEBUG
2863  snprintf(UartBuffer,UARTBUFFERSIZE," %d PCT = Min..Max\r\n",Port);
2864  UartWrite(UartBuffer);
2865  #endif
2866  UartPort[Port].InfoData |= INFODATA_INFO_PCT;
2867  }
2868  }
2869  else
2870  { // Mode invalid
2871  #ifdef DEBUG_D_UART_ERROR
2872  snprintf(UartBuffer,UARTBUFFERSIZE," f %d PCT = Min..Max\r\n",Port);
2873  UartWrite(UartBuffer);
2874  #endif
2875  UartPort[Port].State = UART_INFO_ERROR;
2876  }
2877  }
2878  break;
2879 
2880  case INFO_SI :
2881  { // SI unit scaling values
2882 
2883  TmpL = 0;
2884  for (Tmp = 0;(Tmp < UartPort[Port].InLength) && (Tmp < 4);Tmp++)
2885  {
2886  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp] << (8 * Tmp);
2887  }
2888  *((ULONG*)&TypeData[Port][Mode].SiMin) = TmpL;
2889  TmpL = 0;
2890  for (Tmp = 0;(Tmp < (UartPort[Port].InLength - 4)) && (Tmp < 4);Tmp++)
2891  {
2892  TmpL |= (ULONG)UartPort[Port].InBuffer[Tmp + 4] << (8 * Tmp);
2893  }
2894  *((ULONG*)&TypeData[Port][Mode].SiMax) = TmpL;
2895 
2896  if (TypeData[Port][Mode].Mode == GET_MODE(UartPort[Port].Cmd))
2897  { // Mode valid
2898 
2899  if ((UartPort[Port].InfoData & INFODATA_INFO_SI))
2900  { // Si already given
2901 
2902  #ifdef DEBUG_D_UART_ERROR
2903  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d SI ALREADY GIVEN\r\n",Port);
2904  UartWrite(UartBuffer);
2905  #endif
2906  UartPort[Port].State = UART_INFO_ERROR;
2907  }
2908  else
2909  {
2910  #ifdef HIGHDEBUG
2911  snprintf(UartBuffer,UARTBUFFERSIZE," %d SI = Min..Max\r\n",Port);
2912  UartWrite(UartBuffer);
2913  #endif
2914  UartPort[Port].InfoData |= INFODATA_INFO_SI;
2915  }
2916  }
2917  else
2918  { // Mode invalid
2919  #ifdef DEBUG_D_UART_ERROR
2920  snprintf(UartBuffer,UARTBUFFERSIZE," f %d SI = Min..Max\r\n",Port);
2921  UartWrite(UartBuffer);
2922  #endif
2923  UartPort[Port].State = UART_INFO_ERROR;
2924  }
2925  }
2926  break;
2927 
2928  case INFO_SYMBOL :
2929  { // Presentation format
2930 
2931  if ((UartPort[Port].InfoData & INFODATA_INFO_SYMBOL))
2932  { // Symbol already given
2933 
2934  #ifdef DEBUG_D_UART_ERROR
2935  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d SYMBOL ALREADY GIVEN\r\n",Port);
2936  UartWrite(UartBuffer);
2937  #endif
2938  UartPort[Port].State = UART_INFO_ERROR;
2939  }
2940  else
2941  {
2942  snprintf((char*)TypeData[Port][Mode].Symbol,SYMBOL_LENGTH + 1,"%s",(char*)UartPort[Port].InBuffer);
2943  #ifdef HIGHDEBUG
2944  snprintf(UartBuffer,UARTBUFFERSIZE," %d SYMBOL = %s\r\n",Port,TypeData[Port][Mode].Symbol);
2945  UartWrite(UartBuffer);
2946  #endif
2947  UartPort[Port].InfoData |= INFODATA_INFO_SYMBOL;
2948  }
2949  }
2950  break;
2951 
2952  case INFO_FORMAT :
2953  { // Data sets and format
2954 
2955  if ((UartPort[Port].InfoData & INFODATA_INFO_FORMAT))
2956  { // Format already given
2957 
2958  #ifdef DEBUG_D_UART_ERROR
2959  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d FORMAT ALREADY GIVEN\r\n",Port);
2960  UartWrite(UartBuffer);
2961  #endif
2962  UartPort[Port].State = UART_INFO_ERROR;
2963  }
2964  else
2965  {
2966  TypeData[Port][Mode].DataSets = UartPort[Port].InBuffer[0];
2967  TypeData[Port][Mode].Format = UartPort[Port].InBuffer[1];
2968 
2969 
2970  if (TypeData[Port][Mode].DataSets > 0)
2971  { // Data sets valid
2972 
2973  if (UartPort[Port].Types)
2974  { // Modes left
2975 
2976  UartPort[Port].Types--;
2977  if (TypeData[Port][Mode].Mode == GET_MODE(UartPort[Port].Cmd))
2978  { // Mode valid
2979 
2980  if (UartPort[Port].InLength >= 4)
2981  { // Figures and decimals present
2982 
2983  UartPort[Port].InfoData |= INFODATA_INFO_FORMAT;
2984 
2985  if ((UartPort[Port].InfoData & INFODATA_NEEDED) == INFODATA_NEEDED)
2986  {
2987  snprintf((char*)TypeData[Port][Mode].Name,TYPE_NAME_LENGTH + 1,"%s",(char*)UartPort[Port].Name);
2988 
2989  TypeData[Port][Mode].Type = UartPort[Port].Type;
2990  TypeData[Port][Mode].Connection = CONN_INPUT_UART;
2991  TypeData[Port][Mode].Views = UartPort[Port].Views;
2992 
2993  TypeData[Port][Mode].Figures = UartPort[Port].InBuffer[2];
2994  TypeData[Port][Mode].Decimals = UartPort[Port].InBuffer[3];
2995 
2997  if (TypeData[Port][Mode].Type == 33)
2998  {
2999  TypeData[Port][Mode].InvalidTime = 1100;
3000  }
3001 
3002  Changed[Port][Mode] = 1;
3003  #ifdef HIGHDEBUG
3004  snprintf(UartBuffer,UARTBUFFERSIZE," %d FORMAT = %u * %u %u.%u\r\n",Port,TypeData[Port][Mode].DataSets,TypeData[Port][Mode].Format,TypeData[Port][Mode].Figures,TypeData[Port][Mode].Decimals);
3005  UartWrite(UartBuffer);
3006  #endif
3007  }
3008  else
3009  { // Not enough info data given
3010  #ifdef DEBUG_D_UART_ERROR
3011  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d NOT ENOUGH INFO GIVEN\r\n",Port);
3012  UartWrite(UartBuffer);
3013  #endif
3014  UartPort[Port].State = UART_INFO_ERROR;
3015 
3016  }
3017  }
3018  else
3019  { // Format invalid
3020  #ifdef DEBUG_D_UART_ERROR
3021  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d FORMAT ERROR\r\n",Port);
3022  UartWrite(UartBuffer);
3023  #endif
3024  UartPort[Port].State = UART_INFO_ERROR;
3025 
3026  }
3027  }
3028  else
3029  { // Mode invalid
3030  #ifdef DEBUG_D_UART_ERROR
3031  snprintf(UartBuffer,UARTBUFFERSIZE," f %d FORMAT = %u * %u %u.%u\r\n",Port,TypeData[Port][Mode].DataSets,TypeData[Port][Mode].Format,TypeData[Port][Mode].Figures,TypeData[Port][Mode].Decimals);
3032  UartWrite(UartBuffer);
3033  #endif
3034  UartPort[Port].State = UART_INFO_ERROR;
3035  }
3036  }
3037  else
3038  { // No more modes left
3039  #ifdef DEBUG_D_UART_ERROR
3040  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d TYPES ERROR\r\n",Port);
3041  UartWrite(UartBuffer);
3042  #endif
3043  UartPort[Port].State = UART_INFO_ERROR;
3044 
3045  }
3046  }
3047  else
3048  { // Data sets invalid
3049  #ifdef DEBUG_D_UART_ERROR
3050  snprintf(UartBuffer,UARTBUFFERSIZE," f %d FORMAT = %u * %u %u.%u\r\n",Port,TypeData[Port][Mode].DataSets,TypeData[Port][Mode].Format,TypeData[Port][Mode].Figures,TypeData[Port][Mode].Decimals);
3051  UartWrite(UartBuffer);
3052  #endif
3053  UartPort[Port].State = UART_INFO_ERROR;
3054  }
3055  }
3056  }
3057  break;
3058 
3059  }
3060  }
3061  break;
3062 
3063  }
3064  }
3065  }
3066 
3067  if (UartPort[Port].Type == UartPortDefault.Type)
3068  {
3069  #ifdef DEBUG_D_UART_ERROR
3070  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d TYPE ERROR\r\n",Port);
3071  UartWrite(UartBuffer);
3072  #endif
3073  UartPort[Port].State = UART_INFO_ERROR;
3074  }
3075  }
3076  break;
3077 
3078  //** ERRORS *******************************************************************
3079 
3080  case UART_CMD_ERROR :
3081  {
3082  UartPort[Port].State = UART_ERROR;
3083  }
3084  break;
3085 
3086  case UART_INFO_ERROR :
3087  {
3088  UartPort[Port].State = UART_ERROR;
3089  }
3090  break;
3091 
3092  default :
3093  {
3094  UartPort[Port].State = UART_MESSAGE_START;
3095  }
3096  break;
3097 
3098  }
3099 
3100  //** END OF INFORMATIONS ******************************************************
3101 
3102  UartPort[Port].Check ^= Byte;
3103  }
3104  }
3105  break;
3106 
3107  //** DATA *********************************************************************
3108 
3109  case UART_DATA :
3110  { // Get device data
3111 
3112  UartPort[Port].InLength = UartPortReadData(Port,&UartPort[Port].Cmd,TmpBuffer,&UartPort[Port].Check,&CrcError);
3113 
3114  if (UartPort[Port].InLength)
3115  {
3116  if (!CrcError)
3117  {
3118  if (UartPort[Port].Initialised == 0)
3119  {
3120  UartPort[Port].Initialised = 1;
3121  }
3122  if (!((*pUart).Status[Port] & UART_PORT_CHANGED))
3123  {
3124  if (UartPort[Port].Mode == GET_MODE(UartPort[Port].Cmd))
3125  {
3126  if (!((*pUart).Status[Port] & UART_DATA_READY))
3127  {
3128  (*pUart).Status[Port] |= UART_DATA_READY;
3129 
3130  #ifdef DEBUG_TRACE_MODE_CHANGE
3131  snprintf(UartBuffer,UARTBUFFERSIZE,"d_uart %d State machine: mode changed to %d\n",Port,UartPort[Port].Mode);
3132  UartWrite(UartBuffer);
3133  #endif
3134  }
3135 
3136 #ifdef DEBUG_TRACE_US
3137  if (Port == 1)
3138  {
3139  if (GET_MODE(UartPort[Port].Cmd) == 1)
3140  {
3141  In = (UWORD)TmpBuffer[0];
3142  In |= (UWORD)TmpBuffer[1] << 8;
3143 
3144  if (In > 1000)
3145  {
3146  if (CrcError)
3147  {
3148  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3149  }
3150  else
3151  {
3152  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3153  }
3154  printk(UartBuffer);
3155 
3156  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
3157  {
3158  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",TmpBuffer[Tmp] & 0xFF);
3159  printk(UartBuffer);
3160  }
3161  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\n",UartPort[Port].Check & 0xFF);
3162  printk(UartBuffer);
3163  }
3164  }
3165  }
3166 #endif
3167 
3168  #ifndef DISABLE_FAST_DATALOG_BUFFER
3169 
3170 
3171  memcpy((void*)(*pUart).Raw[Port][(*pUart).LogIn[Port]],(void*)TmpBuffer,UART_DATA_LENGTH);
3172 
3173  (*pUart).Actual[Port] = (*pUart).LogIn[Port];
3174  (*pUart).Repeat[Port][(*pUart).Actual[Port]] = 0;
3175 
3176  if (++((*pUart).LogIn[Port]) >= DEVICE_LOGBUF_SIZE)
3177  {
3178  (*pUart).LogIn[Port] = 0;
3179  }
3180  #else
3181  memcpy((void*)(*pUart).Raw[Port],(void*)TmpBuffer,UART_DATA_LENGTH);
3182  #endif
3183  if (UartPort[Port].DataErrors)
3184  {
3185  UartPort[Port].DataErrors--;
3186  }
3187  UartPort[Port].DataOk = 1;
3188  }
3189  else
3190  {
3191  UartPort[Port].ChangeMode = 1;
3192  }
3193  }
3194  }
3195  else
3196  {
3197  #ifdef DEBUG_D_UART_ERROR
3198  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3199  UartWrite(UartBuffer);
3200 
3201  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
3202  {
3203  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",TmpBuffer[Tmp] & 0xFF);
3204  UartWrite(UartBuffer);
3205  }
3206  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
3207  UartWrite(UartBuffer);
3208  #endif
3209  #ifndef DISABLE_UART_DATA_ERROR
3210  if (++UartPort[Port].DataErrors >= UART_ALLOWABLE_DATA_ERRORS)
3211  {
3212  #ifdef DEBUG_D_UART_ERROR
3213  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d No valid data in %d messages\r\n",Port,UartPort[Port].DataErrors);
3214  UartWrite(UartBuffer);
3215  #endif
3216  UartPort[Port].State = UART_DATA_ERROR;
3217  }
3218  #endif
3219  }
3220  #ifdef DEBUG_TRACE_ANGLE
3221  if (Port == 1)
3222  {
3223  Angle = (UWORD)(*pUart).Raw[Port][0];
3224  Angle |= (UWORD)(*pUart).Raw[Port][1] << 8;
3225 
3226  if (Angle > 50)
3227  {
3228  printk("Angle = %u\r",Angle);
3229  if (CrcError)
3230  {
3231  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3232  }
3233  else
3234  {
3235  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3236  }
3237  printk(UartBuffer);
3238 
3239  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
3240  {
3241  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",TmpBuffer[Tmp] & 0xFF);
3242  printk(UartBuffer);
3243  }
3244  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
3245  printk(UartBuffer);
3246  }
3247  }
3248  #endif
3249 
3250  #ifdef DEBUG
3251  if (ShowTimer[Port] >= (UART_SHOW_TIME / UART_TIMER_RESOLUTION))
3252  {
3253  ShowTimer[Port] = 0;
3254  if (CrcError)
3255  {
3256  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3257  }
3258  else
3259  {
3260  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3261  }
3262  UartWrite(UartBuffer);
3263 
3264  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
3265  {
3266  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",TmpBuffer[Tmp] & 0xFF);
3267  UartWrite(UartBuffer);
3268  }
3269  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
3270  UartWrite(UartBuffer);
3271  }
3272  #endif
3273  }
3274 
3275  if (UartPort[Port].ChangeMode)
3276  { // Try to change mode
3277 
3278  if (UartPort[Port].OutPointer >= UartPort[Port].OutLength)
3279  { // Transmitter ready
3280 
3281  #ifdef DEBUG
3282  ShowTimer[Port] = 0;
3283  if (CrcError)
3284  {
3285  snprintf(UartBuffer,UARTBUFFERSIZE," c %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3286  }
3287  else
3288  {
3289  snprintf(UartBuffer,UARTBUFFERSIZE," %d %02X[",Port,UartPort[Port].Cmd & 0xFF);
3290  }
3291  UartWrite(UartBuffer);
3292 
3293  for (Tmp = 0;Tmp < UartPort[Port].InLength;Tmp++)
3294  {
3295  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",TmpBuffer[Tmp] & 0xFF);
3296  UartWrite(UartBuffer);
3297  }
3298  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].Check & 0xFF);
3299  UartWrite(UartBuffer);
3300  #endif
3301  UartPort[Port].Cmd = UartPort[Port].Mode;
3302  UartPort[Port].OutBuffer[0] = MAKE_CMD_COMMAND(CMD_SELECT,0);
3303  UartPort[Port].OutBuffer[1] = UartPort[Port].Mode;
3304  UartPort[Port].OutBuffer[2] = 0xFF ^ UartPort[Port].OutBuffer[0] ^ UartPort[Port].OutBuffer[1];
3305  UartPort[Port].OutPointer = 0;
3306  UartPort[Port].OutLength = 3;
3307 
3308  UartPort[Port].ChangeMode = 0;
3309 
3310  #ifdef DEBUG_TRACE_MODE_CHANGE
3311  snprintf(UartBuffer,UARTBUFFERSIZE," WR %d %02X[",Port,UartPort[Port].OutBuffer[0]);
3312  UartWrite(UartBuffer);
3313 
3314  for (Tmp = 1;Tmp < (UartPort[Port].OutLength - 1);Tmp++)
3315  {
3316  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].OutBuffer[Tmp] & 0xFF);
3317  UartWrite(UartBuffer);
3318  }
3319  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].OutBuffer[Tmp] & 0xFF);
3320  UartWrite(UartBuffer);
3321  #endif
3322  }
3323  (*pUart).Status[Port] &= ~UART_DATA_READY;
3324  }
3325  if (++UartPort[Port].WatchDog >= (UART_WATCHDOG_TIME / UART_TIMER_RESOLUTION))
3326  { // Try to service watch dog
3327 
3328  if (UartPort[Port].OutPointer >= UartPort[Port].OutLength)
3329  { // Transmitter ready
3330 
3331  UartPort[Port].WatchDog = 0;
3332 
3333  if (!UartPort[Port].DataOk)
3334  { // No ok data since last watch dog service
3335 
3336  #ifndef DISABLE_UART_DATA_ERROR
3337  if (++UartPort[Port].DataErrors >= UART_ALLOWABLE_DATA_ERRORS)
3338  {
3339  #ifdef DEBUG_D_UART_ERROR
3340  snprintf(UartBuffer,UARTBUFFERSIZE," ## %d No valid data in %d services\r\n",Port,UART_ALLOWABLE_DATA_ERRORS);
3341  UartWrite(UartBuffer);
3342  #endif
3343  UartPort[Port].State = UART_DATA_ERROR;
3344  }
3345  else
3346  {
3347  UartPort[Port].DataOk = 1;
3348  }
3349  #else
3350  UartPort[Port].DataOk = 1;
3351  #endif
3352  }
3353  if (UartPort[Port].DataOk)
3354  {
3355  UartPort[Port].DataOk = 0;
3356 
3357  UartPort[Port].OutBuffer[0] = BYTE_NACK;
3358  UartPort[Port].OutPointer = 0;
3359  UartPort[Port].OutLength = 1;
3360  #ifdef DEBUG
3361  snprintf(UartBuffer,UARTBUFFERSIZE," WD %d %02X\r\n",Port,UartPort[Port].OutBuffer[0]);
3362  UartWrite(UartBuffer);
3363  #endif
3364  }
3365  }
3366  }
3367 
3368  if (WriteRequest[Port])
3369  { // Try to write message
3370 
3371  if (UartPort[Port].OutPointer >= UartPort[Port].OutLength)
3372  { // Transmitter ready
3373 
3374  // convert length to length code
3375  Byte = 0;
3376  Tmp = CONVERT_LENGTH(Byte);
3377  while ((Tmp < UART_DATA_LENGTH) && (Tmp < (*pUart).OutputLength[Port]))
3378  {
3379  Byte++;
3380  Tmp = CONVERT_LENGTH(Byte);
3381  }
3382 
3383  Chksum = 0xFF;
3384 
3385  UartPort[Port].OutBuffer[0] = MAKE_CMD_COMMAND(CMD_WRITE,Byte);
3386  Chksum ^= UartPort[Port].OutBuffer[0];
3387 
3388  Pointer = 0;
3389  while (Pointer < Tmp)
3390  {
3391  if (Pointer < (*pUart).OutputLength[Port])
3392  {
3393  UartPort[Port].OutBuffer[1 + Pointer] = (*pUart).Output[Port][Pointer];
3394  }
3395  else
3396  {
3397  UartPort[Port].OutBuffer[1 + Pointer] = 0;
3398  }
3399  Chksum ^= UartPort[Port].OutBuffer[1 + Pointer];
3400  Pointer++;
3401 
3402  }
3403  UartPort[Port].OutBuffer[1 + Pointer] = Chksum;
3404  UartPort[Port].OutPointer = 0;
3405  UartPort[Port].OutLength = Tmp + 2;
3406 
3407  WriteRequest[Port] = 0;
3408  (*pUart).Status[Port] &= ~UART_WRITE_REQUEST;
3409  #ifdef DEBUG
3410  snprintf(UartBuffer,UARTBUFFERSIZE," WR %d %02X[",Port,UartPort[Port].OutBuffer[0]);
3411  UartWrite(UartBuffer);
3412 
3413  for (Tmp = 1;Tmp < (UartPort[Port].OutLength - 1);Tmp++)
3414  {
3415  snprintf(UartBuffer,UARTBUFFERSIZE,"%02X",UartPort[Port].OutBuffer[Tmp] & 0xFF);
3416  UartWrite(UartBuffer);
3417  }
3418  snprintf(UartBuffer,UARTBUFFERSIZE,"]%02X\r\n",UartPort[Port].OutBuffer[Tmp] & 0xFF);
3419  UartWrite(UartBuffer);
3420  #endif
3421  }
3422  }
3423 
3424  #ifndef DISABLE_FAST_DATALOG_BUFFER
3425  ((*pUart).Repeat[Port][(*pUart).Actual[Port]])++;
3426  #endif
3427  }
3428  break;
3429 
3430  case UART_ACK_WAIT :
3431  {
3432  if (++(UartPort[Port].Timer) >= (UART_ACK_DELAY / UART_TIMER_RESOLUTION))
3433  {
3434  (*pUart).Status[Port] |= UART_PORT_CHANGED;
3435  UartPortSend(Port,BYTE_ACK);
3436  UartPort[Port].Timer = 0;
3437  UartPort[Port].State = UART_ACK_INFO;
3438 #ifdef DEBUG_D_UART_ERROR
3439  snprintf(UartBuffer,UARTBUFFERSIZE," %d Type %-3d has changed modes: ",Port,TypeData[Port][0].Type);
3440  UartWrite(UartBuffer);
3441  for (Mode = 0;Mode < MAX_DEVICE_MODES;Mode++)
3442  {
3443  UartBuffer[Mode] = Changed[Port][Mode] + '0';
3444  }
3445  UartBuffer[Mode++] = '\r';
3446  UartBuffer[Mode++] = '\n';
3447  UartBuffer[Mode] = 0;
3448  UartWrite(UartBuffer);
3449 #endif
3450  }
3451  }
3452  break;
3453 
3454  case UART_ACK_INFO :
3455  {
3456  if (++(UartPort[Port].Timer) >= (UART_CHANGE_BITRATE_DELAY / UART_TIMER_RESOLUTION))
3457  {
3458  UartPort[Port].DataOk = 1;
3459  UartPort[Port].DataErrors = 0;
3460  UartPort[Port].Mode = 0;
3461  UartPort[Port].BitRate = UartPort[Port].BitRateMax;
3462  UartPortSetup(Port,UartPort[Port].BitRate);
3463  UartPort[Port].WatchDog = (UART_WATCHDOG_TIME / UART_TIMER_RESOLUTION);
3464  UartPort[Port].State = UART_DATA;
3465  }
3466  }
3467  break;
3468 
3469  case UART_TERMINAL :
3470  {
3471  }
3472  break;
3473 
3474  case UART_DATA_ERROR :
3475  {
3476  UartPort[Port].State = UART_ERROR;
3477  }
3478  break;
3479 
3480  case UART_ERROR :
3481  {
3482  }
3483  break;
3484 
3485  case UART_EXIT :
3486  {
3487  UartPortDisable(Port);
3488  UartPort[Port] = UartPortDefault;
3489 
3490 
3491  for (Tmp = 0;Tmp < MAX_DEVICE_MODES;Tmp++)
3492  {
3493  TypeData[Port][Tmp].Name[0] = 0;
3494  TypeData[Port][Tmp].Type = 0;
3495  Changed[Port][Tmp] = 0;
3496  }
3497  (*pUart).Status[Port] = 0;
3498 
3499  UartPort[Port].State = UART_IDLE;
3500  }
3501  break;
3502 
3503  }
3504  if (UartPort[Port].OutPointer < UartPort[Port].OutLength)
3505  {
3506  if (UartPortSend(Port,UartPort[Port].OutBuffer[UartPort[Port].OutPointer]))
3507  {
3508  UartPort[Port].OutPointer++;
3509  }
3510  }
3511 
3512  }
3513  else
3514  {
3515  switch (UartPort[Port].State)
3516  { // Test state machine
3517 
3518  case UART_IDLE :
3519  { // Port inactive
3520 
3521  }
3522  break;
3523 
3524  case UART_INIT :
3525  { // Initialise port hardware
3526 
3527  UartPortDisable(Port);
3528  PUARTFloat(Port,INPUT_UART_PIN5);
3529  PUARTFloat(Port,INPUT_UART_PIN6);
3530  UartPort[Port].State = UART_ENABLE;
3531  }
3532  break;
3533 
3534  case UART_ENABLE :
3535  { // Initialise port variables
3536 
3537  UartPortEnable(Port);
3538  UartPortSetup(Port,UartPort[Port].BitRate);
3539  (*pUart).Status[Port] = 0;
3540  UartPortFlush(Port);
3541  UartPort[Port].InPointer = 0;
3542  UartPort[Port].State = UART_MESSAGE_START;
3543  }
3544  break;
3545 
3546  case UART_MESSAGE_START :
3547  {
3548  if (UartPort[Port].OutPointer < UartPort[Port].OutLength)
3549  {
3550  if (UartPortSend(Port,UartPort[Port].OutBuffer[UartPort[Port].OutPointer]))
3551  {
3552  UartPort[Port].OutPointer++;
3553  }
3554  }
3555  if (UartPortReceive(Port,&Byte))
3556  {
3557 #ifdef HIGHDEBUG
3558  snprintf(UartBuffer,UARTBUFFERSIZE,"[0x%02X]\r\n",Byte);
3559  UartWrite(UartBuffer);
3560 #endif
3561  if (UartPort[Port].InPointer < UART_BUFFER_SIZE)
3562  {
3563  UartPort[Port].InBuffer[UartPort[Port].InPointer] = Byte;
3564  UartPort[Port].InPointer++;
3565  }
3566  }
3567  }
3568  break;
3569 
3570  }
3571 
3572  }
3573 
3574 #ifdef HIGHDEBUG
3575  if (UartPort[Port].OldState != UartPort[Port].State)
3576  {
3577  UartPort[Port].OldState = UartPort[Port].State;
3578  if (UartPort[Port].State != UART_ENABLE)
3579  {
3580  snprintf(UartBuffer,UARTBUFFERSIZE," %d %s\r\n",Port,UartStateText[UartPort[Port].State]);
3581  }
3582  else
3583  {
3584  snprintf(UartBuffer,UARTBUFFERSIZE,"*** %d %s ***\r\n",Port,UartStateText[UartPort[Port].State]);
3585  }
3586  UartWrite(UartBuffer);
3587  }
3588 #endif
3589  }
3590  }
3591 
3592  return (HRTIMER_RESTART);
3593 }
3594 
3595 
3596 static int Device1Ioctl(struct inode *pNode, struct file *File, unsigned int Request, unsigned long Pointer)
3597 {
3598  int Result = 0;
3599  UARTCTL *pUartCtl;
3600  DEVCON DevCon;
3601  DATA8 Port = 0;
3602  DATA8 Mode;
3603 
3604  switch (Request)
3605  {
3606 
3607  case UART_SET_CONN :
3608  {
3609 
3610  copy_from_user((void*)&DevCon,(void*)Pointer,sizeof(DEVCON));
3611 
3612  for (Port = 0;Port < INPUTS;Port++)
3613  {
3614  if (DevCon.Connection[Port] == CONN_INPUT_UART)
3615  {
3616  if (UartConfigured[Port] == 0)
3617  {
3618  UartConfigured[Port] = 1;
3619  UartPort[Port].State = UART_INIT;
3620  }
3621  else
3622  {
3623  if (UartPort[Port].Initialised)
3624  {
3625  if (UartPort[Port].Mode != DevCon.Mode[Port])
3626  {
3627 #ifdef DEBUG_TRACE_MODE_CHANGE
3628  snprintf(UartBuffer,UARTBUFFERSIZE,"d_uart %d Device1Ioctl: Changing to %c\r\n",Port,DevCon.Mode[Port] + '0');
3629  UartWrite(UartBuffer);
3630 #endif
3631  UartPort[Port].Mode = DevCon.Mode[Port];
3632  UartPort[Port].ChangeMode = 1;
3633  (*pUart).Status[Port] &= ~UART_DATA_READY;
3634  }
3635  }
3636  }
3637  }
3638  else
3639  {
3640  (*pUart).Status[Port] &= ~UART_DATA_READY;
3641  if (UartConfigured[Port])
3642  {
3643  UartConfigured[Port] = 0;
3644  UartPort[Port].State = UART_EXIT;
3645  }
3646  }
3647  }
3648 
3649  }
3650  break;
3651 
3652  case UART_READ_MODE_INFO :
3653  {
3654  pUartCtl = (UARTCTL*)Pointer;
3655  Port = (*pUartCtl).Port;
3656  Mode = (*pUartCtl).Mode;
3657 
3658 #ifdef DEBUG
3659  if (TypeData[Port][Mode].Name[0])
3660  {
3661  snprintf(UartBuffer,UARTBUFFERSIZE,"d_uart %d Device1Ioctl: READ Type=%d Mode=%d\r\n",Port,TypeData[Port][Mode].Type,Mode);
3662  UartWrite(UartBuffer);
3663  }
3664 #endif
3665  if ((Mode < MAX_DEVICE_MODES) && (Port < INPUTS))
3666  {
3667  copy_to_user((void*)&(*pUartCtl).TypeData,(void*)&TypeData[Port][Mode],sizeof(TYPES));
3668  if (Changed[Port][Mode] == 0)
3669  {
3670  (*pUartCtl).TypeData.Name[0] = 0;
3671  }
3672  Changed[Port][Mode] = 0;
3673  }
3674  }
3675  break;
3676 
3677  case UART_NACK_MODE_INFO :
3678  {
3679  pUartCtl = (UARTCTL*)Pointer;
3680  Port = (*pUartCtl).Port;
3681  Mode = (*pUartCtl).Mode;
3682 
3683 #ifdef DEBUG
3684  snprintf(UartBuffer,UARTBUFFERSIZE,"d_uart %d Device1Ioctl: NACK Type=%d Mode=%d\r\n",Port,TypeData[Port][Mode].Type,Mode);
3685  UartWrite(UartBuffer);
3686 #endif
3687  if ((Mode < MAX_DEVICE_MODES) && (Port < INPUTS))
3688  {
3689  Changed[Port][Mode] = 1;
3690  }
3691  }
3692  break;
3693 
3694  case UART_CLEAR_CHANGED :
3695  {
3696  pUartCtl = (UARTCTL*)Pointer;
3697  Port = (*pUartCtl).Port;
3698 
3699  (*pUart).Status[Port] &= ~UART_PORT_CHANGED;
3700  }
3701  break;
3702 
3703  }
3704  return (Result);
3705 
3706 }
3707 
3708 
3709 static ssize_t Device1Write(struct file *File,const char *Buffer,size_t Count,loff_t *Data)
3710 {
3711  char Buf[UART_DATA_LENGTH + 1];
3712  DATA8 Port;
3713  int Lng = 0;
3714 
3715  if (Count <= (UART_DATA_LENGTH + 1))
3716  {
3717  copy_from_user(Buf,Buffer,Count);
3718 
3719  Port = Buf[0];
3720  if (Port < INPUTS)
3721  {
3722  Lng = 1;
3723 
3724  while (Lng < Count)
3725  {
3726  (*pUart).Output[Port][Lng - 1] = Buf[Lng];
3727  Lng++;
3728  }
3729  (*pUart).OutputLength[Port] = Lng - 1;
3730  (*pUart).Status[Port] |= UART_WRITE_REQUEST;
3731  WriteRequest[Port] = 1;
3732  }
3733  }
3734  return (Lng);
3735 }
3736 
3737 
3738 static ssize_t Device1Read(struct file *File,char *Buffer,size_t Count,loff_t *Offset)
3739 {
3740  int Lng = 0;
3741 
3742 #ifdef DEBUG_UART_WRITE
3743  if (LogOutPointer != LogPointer)
3744  {
3745  while ((Count--) && (LogOutPointer != LogPointer))
3746  {
3747  Buffer[Lng++] = LogPool[LogOutPointer];
3748  Buffer[Lng] = 0;
3749 
3750  LogOutPointer++;
3751  if (LogOutPointer >= LOGPOOLSIZE)
3752  {
3753  LogOutPointer = 0;
3754  }
3755  }
3756  }
3757  if (Lng == 0)
3758  {
3759  UartBuffer[0] = 0x1B;
3760  UartBuffer[1] = '[';
3761  UartBuffer[2] = '2';
3762  UartBuffer[3] = 'J';
3763  UartBuffer[4] = 0x1B;
3764  UartBuffer[5] = '[';
3765  UartBuffer[6] = 'H';
3766  UartBuffer[7] = 0;
3767  UartWrite(UartBuffer);
3768  UartWrite(UartBuffer);
3769  snprintf(UartBuffer,UARTBUFFERSIZE,"-----------------------------------------------------------------\r\n");
3770  UartWrite(UartBuffer);
3771  snprintf(UartBuffer,UARTBUFFERSIZE," UART DUMP\r\n");
3772  UartWrite(UartBuffer);
3773  snprintf(UartBuffer,UARTBUFFERSIZE,"-----------------------------------------------------------------\r\n");
3774  UartWrite(UartBuffer);
3775  }
3776 #else
3777  int Tmp;
3778  int Port;
3779 
3780  Port = 0;
3781  Tmp = 5;
3782  while ((Count > Tmp) && (Port < INPUTS))
3783  {
3784  if (Port != (INPUTS - 1))
3785  {
3786  Tmp = snprintf(&Buffer[Lng],4,"%2u ",(UWORD)UartPort[Port].State);
3787  }
3788  else
3789  {
3790  Tmp = snprintf(&Buffer[Lng],5,"%2u\r",(UWORD)UartPort[Port].State);
3791  }
3792  Lng += Tmp;
3793  Count -= Tmp;
3794  Port++;
3795  }
3796 #endif
3797 
3798  return (Lng);
3799 }
3800 
3801 
3802 #define SHM_LENGTH (sizeof(UartDefault))
3803 #define NPAGES ((SHM_LENGTH + PAGE_SIZE - 1) / PAGE_SIZE)
3804 static void *kmalloc_ptr;
3805 
3806 static int Device1Mmap(struct file *filp, struct vm_area_struct *vma)
3807 {
3808  int ret;
3809 
3810  ret = remap_pfn_range(vma,vma->vm_start,virt_to_phys((void*)((unsigned long)pUart)) >> PAGE_SHIFT,vma->vm_end-vma->vm_start,PAGE_SHARED);
3811 
3812  if (ret != 0)
3813  {
3814  ret = -EAGAIN;
3815  }
3816 
3817  return (ret);
3818 }
3819 
3820 
3821 static const struct file_operations Device1Entries =
3822 {
3823  .owner = THIS_MODULE,
3824  .read = Device1Read,
3825  .write = Device1Write,
3826  .mmap = Device1Mmap,
3827  .ioctl = Device1Ioctl,
3828 };
3829 
3830 
3831 static struct miscdevice Device1 =
3832 {
3833  MISC_DYNAMIC_MINOR,
3834  DEVICE1_NAME,
3835  &Device1Entries
3836 };
3837 
3838 
3839 
3840 
3841 
3842 static int Device1Init(void)
3843 {
3844  int Result = 0;
3845  UWORD *pTmp;
3846  int i;
3847  int Tmp;
3848 
3849  Result = misc_register(&Device1);
3850  if (Result)
3851  {
3852  printk(" %s device register failed\n",DEVICE1_NAME);
3853  }
3854  else
3855  {
3856  // allocate kernel shared memory for uart values (pUart)
3857  if ((kmalloc_ptr = kmalloc((NPAGES + 2) * PAGE_SIZE, GFP_KERNEL)) != NULL)
3858  {
3859  pTmp = (UWORD*)((((unsigned long)kmalloc_ptr) + PAGE_SIZE - 1) & PAGE_MASK);
3860  for (i = 0; i < NPAGES * PAGE_SIZE; i += PAGE_SIZE)
3861  {
3862  SetPageReserved(virt_to_page(((unsigned long)pTmp) + i));
3863  }
3864  pUart = (UART*)pTmp;
3865  memset(pUart,0,sizeof(UART));
3866 
3867  Result += Uart1Init();
3868  Result += Uart2Init();
3869 #ifndef DISABLE_PRU_UARTS
3870  Result += Uart3Init();
3871  Result += Uart4Init();
3872 #endif
3873 
3874  for (Tmp = 0;Tmp < INPUTS;Tmp++)
3875  {
3876  UartPort[Tmp] = UartPortDefault;
3877  UartConfigured[Tmp] = 0;
3878 
3879  if (Tmp == DEBUG_UART)
3880  {
3881  UartPort[Tmp].BitRate = 115200;
3882  UartPortSetup(Tmp,UartPort[Tmp].BitRate);
3883  TypeData[Tmp][0] = TypeDefaultUart[1];
3884  (*pUart).Status[Tmp] |= UART_PORT_CHANGED;
3885  UartPortEnable(Tmp);
3886 #ifdef DEBUG
3887  snprintf(UartBuffer,UARTBUFFERSIZE," %s debug uart init test\r\n",DEVICE1_NAME);
3888  UartWrite(UartBuffer);
3889 #endif
3890  }
3891  else
3892  {
3893  UartPortDisable(Tmp);
3894  }
3895  }
3896 #ifdef DEBUG
3897  printk(" %s device register succes\n",DEVICE1_NAME);
3898 #endif
3899 
3900  Device1Time = ktime_set(0,UART_TIMER_RESOLUTION * 100000);
3901  hrtimer_init(&Device1Timer,CLOCK_MONOTONIC,HRTIMER_MODE_REL);
3902  Device1Timer.function = Device1TimerInterrupt1;
3903  hrtimer_start(&Device1Timer,Device1Time,HRTIMER_MODE_REL);
3904 #ifdef DEBUG_UART_WRITE
3905  UartBuffer[0] = 0x1B;
3906  UartBuffer[1] = '[';
3907  UartBuffer[2] = '2';
3908  UartBuffer[3] = 'J';
3909  UartBuffer[4] = 0x1B;
3910  UartBuffer[5] = '[';
3911  UartBuffer[6] = 'H';
3912  UartBuffer[7] = 0;
3913  UartWrite(UartBuffer);
3914  snprintf(UartBuffer,UARTBUFFERSIZE,"-----------------------------------------------------------------\r\n");
3915  UartWrite(UartBuffer);
3916  snprintf(UartBuffer,UARTBUFFERSIZE," UART DUMP\r\n");
3917  UartWrite(UartBuffer);
3918  snprintf(UartBuffer,UARTBUFFERSIZE,"-----------------------------------------------------------------\r\n");
3919  UartWrite(UartBuffer);
3920 #endif
3921  }
3922  }
3923 
3924  return (Result);
3925 }
3926 
3927 
3928 static void Device1Exit(void)
3929 {
3930  int Tmp;
3931  UWORD *pTmp;
3932  int i;
3933 
3934  hrtimer_cancel(&Device1Timer);
3935 
3936 #ifndef DISABLE_PRU_UARTS
3937  Uart4Exit();
3938  Uart3Exit();
3939 #endif
3940  Uart2Exit();
3941  Uart1Exit();
3942 
3943 
3944  for (Tmp = 0;Tmp < INPUTS;Tmp++)
3945  {
3946  UartPort[Tmp] = UartPortDefault;
3947 
3948  if (Tmp == DEBUG_UART)
3949  {
3950  UartPortEnable(Tmp);
3951  }
3952  else
3953  {
3954  UartPortDisable(Tmp);
3955  }
3956  }
3957  if (Tmp == DEBUG_UART)
3958  {
3959  UartPortEnable(0);
3960  }
3961 #ifdef DEBUG
3962  printk(" %s debug uart exit test\r\n",DEVICE1_NAME);
3963 #endif
3964 
3965  // free shared memory
3966  pTmp = (UWORD*)pUart;
3967  pUart = &UartDefault;
3968 
3969  for (i = 0; i < NPAGES * PAGE_SIZE; i+= PAGE_SIZE)
3970  {
3971  ClearPageReserved(virt_to_page(((unsigned long)pTmp) + i));
3972 #ifdef DEBUG
3973  printk(" %s memory page %d unmapped\n",DEVICE1_NAME,i);
3974 #endif
3975  }
3976  kfree(kmalloc_ptr);
3977 
3978  misc_deregister(&Device1);
3979 #ifdef DEBUG
3980  printk(" %s device unregistered\n",DEVICE1_NAME);
3981 #endif
3982  for (Tmp = 0;Tmp < INPUTS;Tmp++)
3983  {
3984  if (Base[Tmp] != NULL)
3985  {
3986  iounmap(Base[Tmp]);
3987  }
3988  }
3989 #ifdef DEBUG
3990  printk(" %s memory unmapped\n",DEVICE1_NAME);
3991 #endif
3992 
3993 }
3994 
3995 
3996 // DEVICE2 ********************************************************************
3997 
3998 #define BUFFER_LNG 16
3999 
4000 static int Device2Ioctl(struct inode *pNode, struct file *File, unsigned int Request, unsigned long Pointer)
4001 {
4002  int Result = 0;
4003  TSTUART Tstuart;
4004  DATA8 Poi;
4005  UBYTE Port;
4006 
4007  copy_from_user((void*)&Tstuart,(void*)Pointer,sizeof(TSTUART));
4008  Port = Tstuart.Port;
4009 
4010  switch (Request)
4011  {
4012  case TST_UART_OFF :
4013  { // Normal mode
4014 
4015  for (Port = 0;Port < INPUTS;Port++)
4016  {
4017  (*pUart).Status[Port] &= ~UART_DATA_READY;
4018  UartPort[Port].State = UART_EXIT;
4019  }
4020  TestMode = 0;
4021  }
4022  break;
4023 
4024  case TST_UART_ON :
4025  { // Test mode
4026 
4027  TestMode = 1;
4028  for (Port = 0;Port < INPUTS;Port++)
4029  {
4030  UartPortDisable(Port);
4031  UartPort[Port] = UartPortDefault;
4032  (*pUart).Status[Port] = 0;
4033  UartPort[Port].State = UART_IDLE;
4034  }
4035  }
4036  break;
4037 
4038  case TST_UART_EN :
4039  {
4040  for (Port = 0;Port < INPUTS;Port++)
4041  {
4042  UartPort[Port] = UartPortDefault;
4043  UartPort[Port].BitRate = Tstuart.Bitrate;
4044  UartPort[Port].State = UART_INIT;
4045  }
4046  }
4047  break;
4048 
4049  case TST_UART_DIS :
4050  {
4051  for (Port = 0;Port < INPUTS;Port++)
4052  {
4053  (*pUart).Status[Port] &= ~UART_DATA_READY;
4054  UartPort[Port].State = UART_EXIT;
4055  }
4056  }
4057  break;
4058 
4059  case TST_UART_WRITE :
4060  { // Write data to uart
4061 
4062  for (Poi = 0;(Poi < Tstuart.Length) && (Poi < UART_BUFFER_SIZE);Poi++)
4063  {
4064  UartPort[Port].OutBuffer[Poi] = Tstuart.String[Poi];
4065  }
4066  UartPort[Port].OutPointer = 0;
4067  UartPort[Port].OutLength = (DATA8)Poi;
4068  }
4069  break;
4070 
4071  case TST_UART_READ :
4072  { // Read data from uart
4073 
4074  for (Poi = 0;(Poi < UartPort[Port].InPointer) && (Poi < Tstuart.Length) && (Poi < UART_BUFFER_SIZE);Poi++)
4075  {
4076  Tstuart.String[Poi] = UartPort[Port].InBuffer[Poi];
4077  }
4078 
4079  copy_to_user((void*)Pointer,(void*)&Tstuart,sizeof(TSTUART));
4080 
4081  UartPort[Port].InPointer = 0;
4082  }
4083  break;
4084 
4085  }
4086  return (Result);
4087 }
4088 
4089 
4090 static ssize_t Device2Write(struct file *File,const char *Buffer,size_t Count,loff_t *Data)
4091 {
4092  int Lng = 0;
4093 
4094  return (Lng);
4095 }
4096 
4097 
4098 static ssize_t Device2Read(struct file *File,char *Buffer,size_t Count,loff_t *Offset)
4099 {
4100  int Lng = 0;
4101 
4102  return (Lng);
4103 }
4104 
4105 
4106 static const struct file_operations Device2Entries =
4107 {
4108  .owner = THIS_MODULE,
4109  .read = Device2Read,
4110  .write = Device2Write,
4111  .ioctl = Device2Ioctl
4112 };
4113 
4114 
4115 static struct miscdevice Device2 =
4116 {
4117  MISC_DYNAMIC_MINOR,
4118  DEVICE2_NAME,
4119  &Device2Entries
4120 };
4121 
4122 
4123 static int Device2Init(void)
4124 {
4125  int Result = -1;
4126 
4127  Result = misc_register(&Device2);
4128  if (Result)
4129  {
4130  printk(" %s device register failed\n",DEVICE2_NAME);
4131  }
4132  else
4133  {
4134 #ifdef DEBUG
4135  printk(" %s device register succes\n",DEVICE2_NAME);
4136 #endif
4137  }
4138 
4139  return (Result);
4140 }
4141 
4142 
4143 static void Device2Exit(void)
4144 {
4145  misc_deregister(&Device2);
4146 #ifdef DEBUG
4147  printk(" %s device unregistered\n",DEVICE2_NAME);
4148 #endif
4149 }
4150 
4151 
4152 // MODULE *********************************************************************
4153 
4154 
4155 #ifndef PCASM
4156 module_param (HwId, charp, 0);
4157 #endif
4158 
4159 static int ModuleInit(void)
4160 {
4161  Hw = HWID;
4162 
4163  if (Hw < PLATFORM_START)
4164  {
4165  Hw = PLATFORM_START;
4166  }
4167  if (Hw > PLATFORM_END)
4168  {
4169  Hw = PLATFORM_END;
4170  }
4171 
4172 #ifdef DEBUG
4173  printk("%s init started\n",MODULE_NAME);
4174 #endif
4175 
4176  if (request_mem_region(DA8XX_GPIO_BASE,0xD8,MODULE_NAME) >= 0)
4177  {
4178  GpioBase = (void*)ioremap(DA8XX_GPIO_BASE,0xD8);
4179  if (GpioBase != NULL)
4180  {
4181 #ifdef DEBUG
4182  printk("%s gpio address mapped\n",MODULE_NAME);
4183 #endif
4184 
4185  InitGpio();
4186 
4187 #ifndef DISABLE_PRU_UARTS
4188  lego_pru_suart_init();
4189 #endif
4190 
4191  Device1Init();
4192  Device2Init();
4193 
4194  }
4195  }
4196 
4197  return (0);
4198 }
4199 
4200 
4201 static void ModuleExit(void)
4202 {
4203 #ifdef DEBUG
4204  printk("%s exit started\n",MODULE_NAME);
4205 #endif
4206 
4207  Device2Exit();
4208  Device1Exit();
4209 
4210 #ifndef DISABLE_PRU_UARTS
4211  lego_pru_suart_exit();
4212 #endif
4213 
4214  iounmap(GpioBase);
4215 }
4216 
4217 
PUARTHigh
#define PUARTHigh(port, pin)
Definition: d_uart_mod.c:904
PUARTLow
#define PUARTLow(port, pin)
Definition: d_uart_mod.c:909
TSTUART::Bitrate
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Definition: lms2012.h:1196
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Definition: d_uart_mod.c:452
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Definition: am1808.h:235
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Definition: d_uart_mod.c:1900
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Data is ready.
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Device type.
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Basic Type used to symbolise 8 bit signed values.
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Schematics revision D.
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Final prototype.
Definition: lms2012.h:101
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Basic Type used to symbolise 32 bit unsigned values.
Definition: lmstypes.h:31
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Definition: d_uart_mod.c:1952
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Definition: d_uart_mod.c:458
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Definition: d_uart_mod.c:570
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Definition: d_uart_mod.c:936
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Definition: d_uart_mod.c:461
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Definition: d_uart_mod.c:937
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Definition: d_uart_mod.c:938
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Definition: lms2012.h:1078
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Definition: lms2012.h:1207
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Definition: am1808.h:224
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Definition: d_uart_mod.c:1843
SYMBOL_LENGTH
#define SYMBOL_LENGTH
Symbol leng th (not including zero)
Definition: lms2012.h:769
UART_ACK_DELAY
#define UART_ACK_DELAY
Definition: d_uart_mod.c:1961
TSTUART::String
DATA8 String[TST_UART_LENGTH]
Definition: lms2012.h:1199
WriteRequest
UBYTE WriteRequest[INPUTS]
Definition: d_uart_mod.c:2243
lego_ti_omapl_pru_suart.h
UART_NACK_MODE_INFO
#define UART_NACK_MODE_INFO
Definition: lms2012.h:1077
pInputUartPin
INPIN * pInputUartPin[]
Definition: d_uart_mod.c:771
lego_pru_uart_activate
int lego_pru_uart_activate(int port)
Definition: lego_ti_omapl_pru_suart.c:1186
module_init
module_init(ModuleInit)
TYPES::Connection
DATA8 Connection
Definition: lms2012.h:778
UART_ENABLE
Definition: d_uart_mod.c:1846
GP1_15
Definition: am1808.h:34
UARTPORT::SubState
UBYTE SubState
Definition: d_uart_mod.c:1902
UART_DATA_COPY
Definition: d_uart_mod.c:1853
UART_TERMINAL_DELAY
#define UART_TERMINAL_DELAY
Definition: d_uart_mod.c:1959
UARTPORT::Types
UBYTE Types
Definition: d_uart_mod.c:1906
FINALB
#define FINALB
Schematics revision B and C.
Definition: lms2012.h:100
UART_ERROR
Definition: d_uart_mod.c:1860
INFODATA_INIT
#define INFODATA_INIT
Definition: d_uart_mod.c:1824
UART_EXIT
Definition: d_uart_mod.c:1861
UartBaseAddr
unsigned long UartBaseAddr[]
Definition: d_uart_mod.c:602
DEVCON::Mode
DATA8 Mode[INPUTS]
Definition: lms2012.h:1062
IntSuccess
UBYTE IntSuccess[INPUTS]
Definition: d_uart_mod.c:926
UARTPORT::OutBuffer
UBYTE OutBuffer[UART_BUFFER_SIZE]
Definition: d_uart_mod.c:1918
UART_CLOCK2
#define UART_CLOCK2
Definition: d_uart_mod.c:928
MODULE_SUPPORTED_DEVICE
MODULE_SUPPORTED_DEVICE(DEVICE1_NAME)
GET_CMD_COMMAND
#define GET_CMD_COMMAND(B)
Definition: d_uart_mod.c:465
UART_TIMER_RESOLUTION
#define UART_TIMER_RESOLUTION
Definition: d_uart_mod.c:1956
omapl_suart_board.h
Uart3
#define Uart3
Definition: d_uart_mod.c:599
UART_READ_MODE_INFO
#define UART_READ_MODE_INFO
Definition: lms2012.h:1076
BYTE_SYNC
#define BYTE_SYNC
Definition: d_uart_mod.c:450
MESSAGE_DATA
#define MESSAGE_DATA
Definition: d_uart_mod.c:457
GP0_13
Definition: am1808.h:33
TYPES::Views
DATA8 Views
Definition: lms2012.h:784
Uart1Base
volatile ULONG * Uart1Base
Definition: d_uart_mod.c:1019
MODULE_AUTHOR
MODULE_AUTHOR("The LEGO Group")
TYPES::DataSets
DATA8 DataSets
Definition: lms2012.h:780
INFODATA_INFO_NAME
#define INFODATA_INFO_NAME
Definition: d_uart_mod.c:1829
Uart2Exit
void Uart2Exit(void)
Definition: d_uart_mod.c:1519
TST_UART_OFF
#define TST_UART_OFF
Definition: lms2012.h:1204
UARTPORT::Type
UBYTE Type
Definition: d_uart_mod.c:1909
PUARTRead
#define PUARTRead(port, pin)
Definition: d_uart_mod.c:901
UART_WRITE_REQUEST
#define UART_WRITE_REQUEST
Write request.
Definition: lms2012.h:1055
pTestPin
INPIN * pTestPin[]
Definition: d_uart_mod.c:779
INPUT_UART_BUFFER
Definition: d_uart_mod.c:576
GP2_7
Definition: am1808.h:35
lego_pru_uart_deactivate
void lego_pru_uart_deactivate(int port)
Definition: lego_ti_omapl_pru_suart.c:1211
UartIntr
int UartIntr[]
Definition: d_uart_mod.c:611
UBYTE
unsigned char UBYTE
Basic Type used to symbolise 8 bit unsigned values.
Definition: lmstypes.h:29
suart_api.h
TYPE_TERMINAL
Port is connected to a terminal.
Definition: lms2012.h:583
UART_FLUSH
Definition: d_uart_mod.c:1847
UART_SET_CONN
#define UART_SET_CONN
Definition: lms2012.h:1075
MODULE_DESCRIPTION
MODULE_DESCRIPTION(MODULE_NAME)
INPIN::Mask
u32 Mask
Definition: am1808.h:226
UWORD
unsigned short UWORD
Basic Type used to symbolise 16 bit unsigned values.
Definition: lmstypes.h:30
UART_RBR
#define UART_RBR
Definition: d_uart_mod.c:931
INFO_PCT
#define INFO_PCT
Definition: d_uart_mod.c:479
Buffer
char Buffer[1024]
Definition: c_wifi.c:102
UART_RECBUF_SIZE
#define UART_RECBUF_SIZE
Definition: d_uart_mod.c:948
UART_IIR
#define UART_IIR
Definition: d_uart_mod.c:934
GET_MESSAGE_LENGTH
#define GET_MESSAGE_LENGTH(B)
Definition: d_uart_mod.c:470
UART_INFO
Definition: d_uart_mod.c:1851
TST_UART_DIS
#define TST_UART_DIS
Definition: lms2012.h:1206
GP1_13
Definition: am1808.h:34
lego_pru_read_bytes
int lego_pru_read_bytes(int port, unsigned char *pdata, int size)
Definition: lego_ti_omapl_pru_suart.c:1311
GP1_14
Definition: am1808.h:34
TYPES::InvalidTime
UWORD InvalidTime
mS from type change to valid data
Definition: lms2012.h:791
UART_THR
#define UART_THR
Definition: d_uart_mod.c:932
UART_DATA
Definition: d_uart_mod.c:1852
UARTPORT::Timer
UWORD Timer
Definition: d_uart_mod.c:1895
INPUT_UART_PIN6
Definition: d_uart_mod.c:580
DEVICE2_NAME
#define DEVICE2_NAME
Definition: d_uart_mod.c:520
UART_DATA_ERROR
Definition: d_uart_mod.c:1859
UartPort
UARTPORT UartPort[INPUTS]
Definition: d_uart_mod.c:1969
UartConfigured
UBYTE UartConfigured[INPUTS]
Definition: d_uart_mod.c:1968
UARTPORT::ChangeMode
UBYTE ChangeMode
Definition: d_uart_mod.c:1899
Uart2
#define Uart2
Definition: d_uart_mod.c:598
TST_UART_WRITE
#define TST_UART_WRITE
Definition: lms2012.h:1208
INFODATA_NEEDED
#define INFODATA_NEEDED
Definition: d_uart_mod.c:1838
TST_UART_EN
#define TST_UART_EN
Definition: lms2012.h:1205
TypeDefaultUart
TYPES TypeDefaultUart[]
Definition: d_uart_mod.c:496
UART_CMD_ERROR
Definition: d_uart_mod.c:1856
UartStateText
char UartStateText[UART_STATES][50]
Definition: d_uart_mod.c:1866
GP0_12
Definition: am1808.h:33
DATA8
SBYTE DATA8
VM Type for 1 byte signed value.
Definition: lmstypes.h:61
GP0_14
Definition: am1808.h:33
suart_err.h
UARTPORT::BitRateMax
ULONG BitRateMax
Definition: d_uart_mod.c:1894
TEST_PINS
Definition: d_uart_mod.c:587
u32
uint32_t u32
Definition: common.h:158
UARTPORT::BitRate
ULONG BitRate
Definition: d_uart_mod.c:1893
UART_TERMINAL
Definition: d_uart_mod.c:1858
CONVERT_LENGTH
#define CONVERT_LENGTH(C)
Definition: d_uart_mod.c:469
UART_INFO_ERROR
Definition: d_uart_mod.c:1857
INFO_SYMBOL
#define INFO_SYMBOL
Definition: d_uart_mod.c:481
UART_PORT_CHANGED
#define UART_PORT_CHANGED
Input port changed.
Definition: lms2012.h:1053
UARTPORT::InPointer
UBYTE InPointer
Definition: d_uart_mod.c:1914
INPUTS
#define INPUTS
Number of input ports in the system.
Definition: lms2012.h:192
Uart1Interrupt
irqreturn_t Uart1Interrupt(int irq, void *dev_id)
Definition: d_uart_mod.c:1032
UART_DLL
#define UART_DLL
Definition: d_uart_mod.c:941
UART_STATES
Definition: d_uart_mod.c:1862
InputUartPins
InputUartPins
Definition: d_uart_mod.c:574
PLATFORM_END
#define PLATFORM_END
Newest supported hardware (newer versions will use this)
Definition: lms2012.h:105
lego_pru_set_baudrate
void lego_pru_set_baudrate(int port, unsigned int baud)
Definition: lego_ti_omapl_pru_suart.c:1250
UART_SYNC
Definition: d_uart_mod.c:1848
INFODATA_CMD_SPEED
#define INFODATA_CMD_SPEED
Definition: d_uart_mod.c:1827
UARTPORT::Mode
UBYTE Mode
Definition: d_uart_mod.c:1908
CMD_WRITE
#define CMD_WRITE
Definition: d_uart_mod.c:464
AXR4
Definition: am1808.h:46
UARTPORT::Initialised
UBYTE Initialised
Definition: d_uart_mod.c:1898
INPUT_UART_RXD
Definition: d_uart_mod.c:578
INFO_NAME
#define INFO_NAME
Definition: d_uart_mod.c:477
Uart4
#define Uart4
Definition: d_uart_mod.c:600
module_exit
module_exit(ModuleExit)
UART_BREAK_TIME
#define UART_BREAK_TIME
Definition: d_uart_mod.c:1958
UARTPORT::InfoData
ULONG InfoData
Definition: d_uart_mod.c:1892
UART_FCR
#define UART_FCR
Definition: d_uart_mod.c:935
lego_pru_suart_init
int lego_pru_suart_init(void)
Definition: lego_ti_omapl_pru_suart.c:1361
PLATFORM_START
#define PLATFORM_START
Oldest supported hardware (older versions will use this)
Definition: lms2012.h:104
UARTPORT::Cmd
UBYTE Cmd
Definition: d_uart_mod.c:1903
NULL
#define NULL
Definition: pru_can_emulation_api.h:37
Base
volatile ULONG * Base[INPUTS]
Definition: d_uart_mod.c:925